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information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or oth - erwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad9995 12-bit ccd signal processor with precision timing ? generator functional block diagram ad9995 cds vga clamp 12-bit adc 12 dclk mshut strobe clocli dout vref 6db t o 42db horizontal drivers v - h control 4 6 5 rg h1Ch4 v1Cv6 vsg1Cvsg5 vrt vrb precision timing generat or sync generat or internal clocks vsub subck hd vd sync internal registers sl sck da ta ccdin features 6-phase vertical transfer clock support correlated double sampler (cds) 6 db to 42 db 10-bit variable gain amplifer (vga) 12-bit 36 mhz a/d converter black level clamp with variable level control complete on-chip timing generator precision timing core with <600 ps resolution on-chip 3 v horizontal and rg drivers 2-phase and 4-phase h-clock modes electronic and mechanical shutter modes on-chip driver for external crystal on-chip sync generator with external sync input 56-lead lfcsp package applications digital still cameras digital video camcorders industrial imaging general description the ad9995 is a highly integrated ccd signal processor for digital still camera and camcorder applications. it includes a complete analog front end with a/d conversion, combined with a full-function programmable timing generator. the timing genera - tor is capable of supporting both 4- and 6-phase vertical clocking. a precision timing core allows adjustment of high speed clocks with less than 600 ps resolution at 36 mhz operation. the ad9995 is specifed at pixel rates of up to 36 mhz. the analog front end includes black level clamping, cds, vga, and a 12-bit a/d converter. the timing generator provides all the necessary ccd clocks: rg, h-clocks, v-clocks, sensor gate pulses, substrate clock, and substrate bias control. operation is programmed using a 3-wire serial interface. packaged in a space-saving 56-lead lfcsp, the ad9995 is speci - fed over an operating temperature range of C20c to +85c. rev. 0 obsolete
ad9995 C2C C3C ad9995Cspecifications table of contents specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 digital specifcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ad9995 analog specifcations . . . . . . . . . . . . . . . . . . . . . . 4 timing specifcations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . 5 package thermal characteristics . . . . . . . . . . . 5 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin function descriptions . . . . . . . . . . . . . . . . . . . 6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance characteristics . . . . . . 8 system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 precision timing high speed timing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 timing resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 high speed clock programmability . . . . . . . . . . . . . . . . . 10 h-driver and rg outputs . . . . . . . . . . . . . . . . . . . . . . . . 11 digital data outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 horizontal clamping and blanking . . . . . . . . 13 individual clpob and pblk patterns . . . . . . . . . . . . . . . 13 individual hblk patterns . . . . . . . . . . . . . . . . . . . . . . . . 13 generating special hblk patterns . . . . . . . . . . . . . . . . . . 14 generating hblk line alternation . . . . . . . . . . . . . . . . . 14 horizontal timing sequence example . . . . . . 15 vertical timing generation . . . . . . . . . . . . . . . . 16 vertical pattern groups (vpat) . . . . . . . . . . . . . . . . . . . . 17 vertical sequences (vseq) . . . . . . . . . . . . . . . . . . . . . . . . 18 complete field: combining v-sequences . . . . . . . . . . . . . 19 generating line alternation for v-sequence and hblk . . 20 second v-pattern group during vsg active line . . . . . . . 20 sweep mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 multiplier mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 vertical sensor gate (shift gate) patterns . . . . . . . . . . . . . 22 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 vertical timing example . . . . . . . . . . . . . . . . . . . . 24 important note about signal polarities . . . . . . . . . . . . . . . 24 shutter timing control . . . . . . . . . . . . . . . . . . . . 26 normal shutter operation . . . . . . . . . . . . . . . . . . . . . . . . 26 high precision shutter operation . . . . . . . . . . . . . . . . . . . 26 low speed shutter operation . . . . . . . . . . . . . . . . . . . . . . 26 subck suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 readout after exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 using the trigger register . . . . . . . . . . . . . . . . . . . . . . 27 vsub control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mshut and strobe control . . . . . . . . . . . . . . . . . . . . 28 trigger register limitations . . . . . . . . . . . . . . . . . . . . 29 exposure and readout example . . . . . . . . . . . . 30 afe description and operation . . . . . . . . . . . . . 31 dc restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 correlated double sampler . . . . . . . . . . . . . . . . . . . . . . . 31 variable gain amplifer . . . . . . . . . . . . . . . . . . . . . . . . . . 31 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 optical black clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 digital data outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 power-up and synchronization . . . . . . . . . . . . . 33 recommended power-up sequence for master mode . . . . 33 generating software sync without external sync signal . . . . . . . . . . . . . . . . . . . . . . . . . 33 sync during master mode operation . . . . . . . . . . . . . . . 34 power-up and synchronization in slave mode . . . . . . . . . 34 standby mode operation . . . . . . . . . . . . . . . . . . . . 34 circuit layout information . . . . . . . . . . . . . . . . 36 serial interface timing . . . . . . . . . . . . . . . . . . . . . 37 register address banks 1 and 2 . . . . . . . . . . . . . . . . . . . . . 38 updating of new register values . . . . . . . . . . . . . . . . . . . . 39 complete listing of register bank 1 . . . . . . . 40 complete listing of register bank 2 . . . . . . . 43 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 59 rev. 0 rev. 0 obsolete
C3 C ad9995Cspecifications parameter min typ max unit temperature range operating C20 +85 c storage C65 +150 c power supply voltage avdd (afe analog supply) 2.7 3.0 3.6 v tcvdd (timing core analog supply) 2.7 3.0 3.6 v rgvdd (rg driver) 2.7 3.0 3.6 v hvdd (h1Ch4 drivers) 2.7 3.0 3.6 v drvdd (data output drivers) 2.7 3.0 3.6 v dvdd (digital) 2.7 3.0 3.6 v power dissipation (see tpc 1 for power curves) 36 mhz, typ supply levels, 100 pf h1Ch4 loading 360 mw power from hvdd only * 130 mw standby 1 mode 130 mw standby 2 mode 12 mw standby 3 mode 0.5 mw maximum clock rate (cli) 36 mhz * the total power dissipated by the hvdd supply may be approximated using the equation total hvdd power hvdd number of h outputs used = [ ] c [ ] c hvdd [ ] hvdd pixel [ ] pixel frequency [ ] frequency load [ ] load = [ ] = c = c [ ] c = c load = load [ ] load = load [ ] hvdd hvdd ? h ? h reducing the h-loading, using only two of the outputs, and/or using a lower hvdd supply will reduce the power dissipation. specif cations subject to change without notice. digital specifications parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs (except h and rg) high level output voltage @ i oh = 2 ma v oh 2.2 v low level output voltage @ i ol = 2 ma ol = 2 ma ol v ol 0.5 v rg and h-driver outputs (h1Ch4) high level output voltage @ max current v oh vdd C 0.5 v low level output voltage @ max current v ol 0.5 v maximum output current (programmable) 30 ma maximum load capacitance (for each output) 100 pf specif cations subject to change without notice. rev. 0 obsolete
C4 C ad9995 analog specifications parameter min typ max unit notes cds * allowable ccd reset transient 500 mv max input range before saturation 1.0 v p-p max ccd black pixel amplitude 50 mv variable gain amplifier (vga) gain control resolution 1024 steps gain monotonicity guaranteed gain range min gain (vga code 0) 6 db max gain (vga code 1023) 42 db black level clamp clamp level resolution 256 steps clamp level measured at adc output. min clamp level (code 0) 0 lsb max clamp level (code 255) 255 lsb a/d converter resolution 12 bits differential nonlinearity (dnl) C1.0 0.5 +1.0 lsb no missing codes guaranteed full-scale input voltage 2.0 v voltage reference reference top voltage (reft) 2.0 v reference bottom voltage (refb) 1.0 v system performance includes entire signal chain. gain accuracy low gain (vga code 0) 5.0 5.5 6.0 db gain = (0.0351 code) + 6 db max gain (vga code 1023) 40.5 41.5 42.5 db peak nonlinearity, 500 mv input signal 0.2 % 12 db gain applied. total output noise 0.8 lsb rms ac grounded input, 6 db gain applied. power supply rejection (psr) 50 db measured with step change on supply. * input signal characteristics def ned as follows: 50mv ma x optical black pixel 500m v ty p reset transient 1v ma x input signal rang e specif cations subject to change without notice. (avdd = 3.0 v, f cli = 36 mhz, typical timing specif cations, t min to t max , unless otherwise noted.) rev. 0 obsolete
ad9995 C5 C timing specifications (c l = 20 pf, avdd = dvdd = drvdd = 3.0 v, f cli = 36 mhz, unless otherwise noted.) parameter symbol min typ max unit master clock, cli (figure 4) cli clock period t conv 27.8 ns cli high/low pulsewidth 11.2 13.9 16.6 ns delay from cli rising edge to internal pixel position 0 t clidly 6 ns afe clpob pulsewidth 1, 2 (figures 9 and 14) 2 20 pixels afe sample location 1 (figure 7) shp sample edge to shd sample edge t s1 12.5 13.9 ns data outputs (figures 8a and 8b) output delay from dclk rising edge 1 t od 8 ns pipeline delay from shp/shd sampling to dout 11 cycles serial interface (figures 40a and 40b) maximum sck frequency f sclk f sclk f 10 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck falling edge to sdata valid hold t dh 10 ns sck falling edge to sdata valid read t dv 10 ns notes 1 parameter is programmable. 2 minimum clpob pulsewidth is for functional operation only. wider typical pulses are recommended to achieve good clamp performance. specif cations subject to change without notice. absolute maximum ratings * with respect parameter to min max unit avdd avss C0.3 +3.9 v tcvdd tcvss C0.3 +3.9 v hvdd hvss C0.3 +3.9 v rgvdd rgvss C0.3 +3.9 v dvdd dvss C0.3 +3.9 v drvdd drvss C0.3 +3.9 v rg output rgvss C0.3 rgvdd + 0.3 v h1Ch4 output hvss C0.3 hvdd + 0.3 v digital outputs dvss C0.3 dvdd + 0.3 v digital inputs dvss C0.3 dvdd + 0.3 v sck, sl, sdata dvss C0.3 dvdd + 0.3 v reft, refb, ccdin avss C0.3 avdd + 0.3 v junction temperature 150 c lead temperature, 10 sec 350 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions above those listed in the operational sections of this specif cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specif ed, all other voltages are referenced to gnd. package thermal characteristics thermal resistance ja = 25c/w * * ja is measured using a 4-layer pcb with the exposed paddle soldered to the board. ordering guide temperature package package model range description option ad9995kcp C20c to +85c lfcsp cp-56 ad9995kcprl C20c to +85c lfcsp cp-56 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily ac cu mu late on the human body and test equipment and can discharge without detection. although the ad9995 features proprietary esd pro tec tion circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pre cau tions are rec om mend ed to avoid per for mance deg ra da tion or loss of functionality. rev. 0 obsolete
ad9995 C6 C pin configuration top view ad9995 pin 1 i dentifier 42 sdi 41 sl 40 refb 39 reft 38 avss 37 ccdin 36 avdd 35 cli 34 clo 33 tcvdd d5 1 d6 2 d7 3 d8 4 d9 5 d10 6 (msb) d11 7 drvdd 8 drvss 9 vsub 10 56 d4 55 d3 54 d2 53 d1 52 d0 (lsb) 51 dclk 50 hd 49 dvdd 48 dvss 47 vd v4 15 v5 16 v6 17 vsg1 18 vsg2 19 vsg3 20 vsg4 21 vsg5 22 h1 23 h2 24 subck 11 v1 12 v2 13 v3 14 hvss 25 hvdd 26 h3 27 h4 28 32 tcvss 31 rgvdd 30 rg 29 rgvss 46 sync_clp 45 strobe 44 mshut 43 sck pin mnemonic type 2 description 1 d5 do data output 2 d6 do data output 3 d7 do data output 4 d8 do data output 5 d9 do data output 6 d10 do data output 7 d11 do data output (msb) 8 drvdd p data output driver supply 9 drvss p data output driver ground 10 vsub do ccd substrate bias 11 subck do ccd substrate clock (e-shutter) 12 v1 do ccd vertical transfer clock 1 13 v2 do ccd vertical transfer clock 2 14 v3 do ccd vertical transfer clock 3 15 v4 do ccd vertical transfer clock 4 16 v5 do ccd vertical transfer clock 5 17 v6 do ccd vertical transfer clock 6 18 vsg1 do ccd sensor gate pulse 1 19 vsg2 do ccd sensor gate pulse 2 20 vsg3 do ccd sensor gate pulse 3 21 vsg4 do ccd sensor gate pulse 4 22 vsg5 do ccd sensor gate pulse 5 23 h1 do ccd horizontal clock 1 24 h2 do ccd horizontal clock 2 25 hvss p h1Ch4 driver ground 26 hvdd p h1Ch4 driver supply 27 h3 do ccd horizontal clock 3 28 h4 do ccd horizontal clock 4 29 rgvss p rg driver ground 30 rg do ccd reset gate clock 31 rgvdd p rg driver supply 32 tcvss p analog ground for timing core 33 tcvdd p analog supply for timing core 34 clo do clock output for crystal 35 cli di reference clock input pin mnemonic type 2 description 36 avdd p analog supply for afe 37 ccdin ai ccd signal input 38 avss p analog ground for afe 39 reft ao voltage reference top bypass 40 refb ao voltage reference bottom bypass 41 sl di 3-wire serial load pulse 42 sdi di 3-wire serial data input 43 sck di 3-wire serial clock 44 mshut do mechanical shutter pulse 45 strobe do strobe pulse 46 sync di external system sync input 47 vd dio vertical sync pulse (input for slave mode, output for master mode) 48 dvss p digital ground 49 dvdd p power supply for vsg, v1Cv6, hd/vd, mshut, strobe, sync, and serial interface 50 hd dio horizontal sync pulse (input for slave mode, output for master mode) 51 dclk do data clock output 52 d0 do data output (lsb) 53 d1 do data output 54 d2 do data output 55 d3 do data output 56 d4 do data output notes 1 see figure 38 for circuit conf guration. 2 ai = analog input, ao = analog output, di = digital input, do = digital output, dio = digital input/output, p = power. pin function descriptions 1 rev. 0 obsolete
ad9995 C7 C terminology differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. therefore, every code must have a f nite width. no missing codes guaran- teed to 12-bit resolution indicates that all 4096 codes must be present over all operating conditions. peak nonlinearity peak nonlinearity, a full signal chain specif cation, refers to the peak deviation of the output of the ad9995 from a true straight line. the point used as zero scale occurs 0.5 lsb before the f rst code transition. positive full scale is def ned as a level 1.5 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the true straight line. the error is then expressed as a percent- age of the 2 v adc full-scale signal. the input signal is always appropriately gained up to f ll the adcs full-scale range. total output noise the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb and represents the rms noise level of the total signal chain at the specif ed gain setting. the output noise can be converted to an equivalent voltage using the relationship 1 lsb = (adc full scale/2 n codes), where n is the bit resolution of the adc. for the ad9995, 1 lsb is 0.488 mv. power supply rejection (psr) the psr is measured with a step change applied to the supply pins. the psr specif cation is calculated from the change in the data outputs for a given step change in the supply voltage. equivalent circuits r avdd avss avss circuit 1. ccdin dvdd dvss drvss drvdd three- sta te data dout circuit 2. digital data outputs dvdd dvss circuit 3. digital inputs hvdd or rgvdd hvss or rgvss output rg, h1Ch4 enable circuit 4. h1Ch4, rg drivers rev. 0 obsolete
C8 C ad9995Ctypical performance characteristics sample rate (mhz) 450 350 150 36 18 power dissipation (mw) 250 300 400 24 v dd = 3.3v v dd = 3.0v v dd = 2.7v 200 30 tpc 1. power dissipation vs. sample rate 0 1000 500 1500 2000 2500 3000 3500 4000 0 C1.0 1.0 C0.5 0.5 codes dnl (lsb) tpc 2. typical dnl performance vga gain code (lsb) 48 0 0 1000 400 200 600 800 output noise (lsb) 16 32 8 24 40 tpc 3. output noise vs. vga gain rev. 0 obsolete
ad9995 C9 C system overview figure 1 shows the typical system block diagram for the ad9995 used in master mode. the ccd output is processed by the ad9995s afe circuitry, which consists of a cds, vga, black level clamp, and a/d converter. the digitized pixel information is sent to the digital image processor chip, which performs the postprocessing and compression. to operate the ccd, all ccd timing parameters are programmed into the ad9995 from the system microprocessor through the 3-wire serial interface. from the system master clock, cli, provided by the image processor or external crystal, the ad9995 generates all of the ccds hori- zontal and vertical clocks and all internal afe clocks. external synchronization is provided by a sync pulse from the micropro- cessor, which will reset internal counters and resync the vd and hd outputs. alternatively, the ad9995 may be operated in slave mode, in which vd and hd are provided externally from the image pro- cessor. in this mode, all ad9995 timing will be synchronized with vd and hd. ccdin mshut strobe h1Ch4, rg, vsub v 1Cv6, vsg1Cvsg5, subck ccd v-driver ad9995 afetg digital image processing asic dout dclk hd, vd cli serial interface sync figure 1. typical system block diagram, master mode the h-drivers for h1Ch4 and rg are included in the ad9995, allowing these clocks to be directly connected to the ccd. h-drive voltage of up to 3.3 v is supported. an external v-driver is required for the vertical transfer clocks, the sensor gate pulses, and the substrate clock. the ad9995 also includes programmable mshut and strobe outputs, which may be used to trigger mechanical shutter and strobe (f ash) circuitry. figures 2 and 3 show the maximum horizontal and vertical counter dimensions for the ad9995. all internal horizontal and vertical clocking is controlled by these counters to specify line and pixel locations. maximum hd length is 4095 pixels per line, and maximum vd length is 4095 lines per f eld. 12-bit horizontal = 4096 pixels max 12-bit vertical = 4096 lines max maximum field dimensions figure 2. vertical and horizontal counters vd hd max vd length is 4095 lines cli max hd length is 4095 pixels figure 3. maximum vd/hd dimensions rev. 0 obsolete
ad9995 C10 C precision timing high speed timing generation the ad9995 generates high speed timing signals using the f exible precision timing core. this core is the foundation for generating the timing used for both the ccd and the afe: the reset gate rg, horizontal drivers h1Ch4, and shp/shd sample clocks. a unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal ccd readout and the afe correlated double sampling. the high speed timing of the ad9995 operates the same in either master or slave mode conf guration. for more information on synchronization and pipeline delays, see the power-up and syn- chronization section. timing resolution the precision timing core uses a 1 master clock input (cli) as a reference. this clock should be the same as the ccd pixel clock frequency. figure 4 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. using a 20 mhz cli frequency, the edge resolution of the preci- sion timing core is 1 ns. if a 1 system clock is not available, it is also possible to use a 2 reference clock by programming the clidivide register (addr. 0x30). the ad9995 will then inter- nally divide the cli frequency by 2. the ad9995 also includes a master clock output, clo, which is the inverse of cli. this output is intended to be used as a crystal driver. a crystal can be placed between the cli and clo pins to generate the master clock for the ad9995. for more information on using a crystal, see figure 39. high speed clock programmability figure 5 shows how the high speed clocks rg, h1Ch4, shp, and shd are generated. the rg pulse has programmable rising and falling edges, and may be inverted using the polarity control. the horizontal clocks h1 and h3 have programmable rising and falling edges and polarity control. the h2 and h4 clocks are always inverses of h1 and h3, respectively. table i summarizes the high speed timing registers and their parameters. figure 6 shows the typical 2-phase h-clock arrangement in which h3 and h4 are programmed for the same edge location as h1 and h2. the edge location registers are 6 bits wide, but there are only 48 valid edge locations available. therefore, the register values are notes pixel clock period is divided into 48 positions, providing fine edge resolu tion for high speed clocks. there is a fixed delay from the cli input to the internal pixel period positi ons ( t clidly = 6ns typ). p[0] p[48] = p[0] p[12] p[24] p[36] 1 pixel period cli t clidly position figure 4. high speed clock resolution from cli master clock input h1 h2 ccd signal rg programmable clock positions: 1. rg rising edge 2. rg falling edge 3. shp sample location 4. shd sample location 5. h1 rising edge position 7. h3 rising edge position h3 h4 3 4 1 2 5 6 7 8 6. h1 falling edge position (h2 is inverse of h1) 8. h3 falling edge position (h4 is inverse of h3) figure 5. high speed clock programmable locations rev. 0 obsolete
ad9995 C1 0C ad9995 C1 1C mapped into four quadrants, with each quadrant containing 12 edge locations. table ii shows the correct register values for the corresponding edge locations. figure 7 shows the default timing locations for all of the high speed clock signals. h-driver and rg outputs in addition to the programmable timing positions, the ad9995 features on-chip output drivers for the rg and h1Ch4 outputs. these drivers are powerful enough to directly drive the ccd inputs. the h-driver and rg current can be adjusted for optimum rise/fall time into a particular load by using the drvcontrol register (addr. 0x35). the 3-bit drive setting for each output is adjustable in 4.1 ma increments, with the minimum setting of 0 equal to off or three-state, and the maximum setting of 7 equal to 30.1 ma. as shown in figures 5, 6, and 7, the h2 and h4 outputs are inverses of h1 and h3, respectively. the h1/h2 crossover volt - age is approximately 50% of the output swing. the crossover voltage is not programmable. digital data outputs the ad9995 data output and dclk phases are programmable using the doutphase register (addr. 0x37, bits [5:0]). any edge from 0 to 47 may be programmed, as shown in figure 8a. normally, the dout and dclk signals will track in phase based on the doutphase register contents. the dclk output phase can also be held fxed with respect to the data out - puts by changing the dclkmode register high (addr. 0x37, bit 6). in this mode, the dclk output will remain at a fxed phase equal to clo (the inverse of cli) while the data output phase is still programmable. there is a fxed output delay from the dclk rising edge to the dout transition, called t od . this delay can be programmed to four values between 0 ns and 12 ns by using the doutdelay register (addr. 0x037, bits [8:7]). the default value is 8 ns. the pipeline delay through the ad9995 is shown in figure 8b. after the ccd input is sampled by shd, there is an 11-cycle delay until the data is available. table i. timing core register parameters for h1, h3, rg, shp/shd parameter length range description polarity 1b high/low polarity control for h1, h3, and rg (0 = no inversion, 1 = inversion) positive edge 6b 0C47 edge location positive edge location for h1, h3, and rg negative edge 6b 0C47 edge location negative edge location for h1, h3, and rg sampling location 6b 0C47 edge location sampling location for internal shp and shd signals drive strength 3b 0C47 current steps drive current for h1Ch4 and rg outputs (4.1 ma per step) h1/h3 h2/h4 rg using the same toggle positions for h1 and h3 generates standard 2-pha se h-clocking. ccd signal figure 6. 2-phase h-clock operation table ii. precision timing edge locations quadrant edge location (dec) register value (dec) register value (bin) i 0 to 11 0 to 11 000000 to 001011 ii 12 to 23 16 to 27 010000 to 011011 iii 24 to 35 32 to 43 100000 to 101011 iv 36 to 47 48 to 59 110000 to 111011 rev. 0 rev. 0 obsolete
ad9995 C12 C p[0] pixel period rg h1/h3 rgf[12] p[48] = p[0] hf[24] ccd signal p[24] p[12] p[36] hr[0] rgr[0] shd[0] notes all signal edges are fully programmable to any of the 48 posi tions within one pixel period. default positions for each signal are shown. position t s1 h2/h4 shp[24] figure 7. high speed timing default locations notes data output (dout) and dclk phase are adjustable with respect to the pixel period. within one clock period, the data transition can be programmed to 48 di fferent locations. output delay ( t od ) from dclk rising edge to dout rising edge is programmable. p[0] p[48] = p[0] pixel period p[12] p[24] p[36] dout dclk t od figure 8a. digital output phase adjustment notes default timing values are shown: shdloc = 0, dout phase = 0, dclkmode = 0. higher values of shd and/or doutphase will shift dout transition to the right, with respect to cli location. dclk dout ccdin cli shd (internal) n n+1 n+2 n+12 n+11 n+10 n+9 n+8 n+7 n+6 n+5 n+4 n+3 n+13 nC13 nC3 nC4 nC5 nC6 nC7 nC8 nC9 nC10 nC11 nC12 nC2 nC1 n+1 n sample pixel n pipeline latency=11 cycles t clidly nC1 n+2 figure 8b. pipeline delay rev. 0 obsolete
ad9995 C1 2C ad9995 C1 3C horizontal clamping and blanking the ad9995s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. individual control is provided for clpob, pblk, and hblk during the different regions of each feld. this allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout in order to accommodate different image transfer timing and high speed line shifts. individual clpob and pblk patterns the afe horizontal timing consists of clpob and pblk, as shown in figure 9. these two signals are independently pro - grammed using the registers in table iii. spol is the start polarity for the signal, and tog1 and tog2 are the frst and second toggle positions of the pulse. both signals are active low and should be programmed accordingly. a separate pattern for clpob and pblk may be programmed for every 10 v-sequences. as described in the vertical timing generation section, up to 10 separate v-sequences can be created, each containing a unique pulse pattern for clpob and pblk. figure 9 shows how the sequence change positions divide the readout feld into different regions. a different v-sequence can be assigned to each region, allowing the clpob and pblk signals to be changed accordingly with each change in the vertical timing. individual hblk patterns the hblk programmable timing shown in figure 10 is simi - lar to clpob and pblk. however, there is no start polarity control. only the toggle positions are used to designate the start and stop positions of the blanking period. additionally, there is a polarity control hblkmask that designates the polarity of the horizontal clock signals h1Ch4 during the blanking period. set - ting hblkmask high will set h1 = h3 = low and h2 = h4 = high during the blanking, as shown in figure 11. as with the clpob and pblk signals, hblk registers are available in each v-sequence, allowing different blanking signals to be used with different vertical timing sequences. (3) (2) (1) hd clpob pblk . . . notes programmable settings: 1. start polarity (clamp and blank region are active low) 2. first toggle position 3. second toggle position . . . active active figure 9. clamp and pre-blank pulse placement table iii. clpob and pblk pattern registers register length range description spol 1b high/low starting polarity of clpob/pblk for v-sequence 0C9 tog1 12b 0C4095 pixel location first toggle position within line for v-sequence 0C9 tog2 12b 0C4095 pixel location second toggle position within line for v-sequence 0C9 table iv. hblk pattern registers register length range description hblkmask 1b high/low masking polarity for h1/h3 (0 = h1/h3 low, 1 = h1/h3 high) hblkalt 2b 0C3 alternation mode enables odd/even alternation of hblk toggle positions 0 = disable alternation. 1 = tog1Ctog2 odd, tog3Ctog6 even. 2 = 3 = tog1Ctog2 even, tog3Ctog6 odd hblktog1 12b 0C4095 pixel location first toggle position within line for each v-sequence 0C9 hblktog2 12b 0C4095 pixel location second toggle position within line for each v-sequence 0C9 hblktog3 12b 0C4095 pixel location third toggle position within line for each v-sequence 0C9 hblktog4 12b 0C4095 pixel location fourth toggle position within line for each v-sequence 0C9 hblktog5 12b 0C4095 pixel location fifth toggle position within line for each v-sequence 0C9 hblktog6 12b 0C4095 pixel location sixth toggle position within line for each v-sequence 0C9 rev. 0 rev. 0 obsolete
ad9995 C14 C generating special hblk patterns there are six toggle positions available for hblk. normally, only two of the toggle positions are used to generate the standard hblk interval. however, the additional toggle positions may be used to generate special hblk patterns, as shown in figure 12. the pattern in this example uses all six toggle positions to gen- erate two extra groups of pulses during the hblk interval. by changing the toggle positions, different patterns can be created. generating hblk line alternation one further feature of the ad9995 is the ability to alternate dif- ferent hblk toggle positions on odd and even lines. this may be used in conjunction with v-pattern odd/even alternation or on its own. when a 1 is written to the hblkalt register, tog1 and tog2 are used on odd lines only, while tog3C tog 6 are used on even lines. writing a 2 to the hblkalt register gives the opposite result: tog1 and tog2 are used on even lines, while tog3Ctog6 are used on odd lines. see the vertical timing generation, line alternation section for more information. hd hblk programmable settings: 1. first toggle position = start of blanking 2. second toggle position = end of blanking blank blank 1 2 figure 10. horizontal blanking (hblk) pulse placement hd hblk the polarity of h1 during blanking is programmable (h2 is opposite polari ty of h1). h1/h3 h1/h3 h2/h4 figure 11. hblk masking control hblk special h-blank pattern is created using multiple hbl k toggle positions. h1/h3 h2/h4 tog1 tog2 tog3 tog4 tog5 tog6 figure 12. generating special hblk patterns rev. 0 obsolete
ad9995 C15 C horizontal timing sequence example figure 13 shows an example ccd layout. the horizontal register contains 28 dummy pixels, which will occur on each line clocked from the ccd. in the vertical direction, there are 10 optical black (ob) lines at the front of the readout and two at the back of the readout. the horizontal direction has four ob pixels in the front and 48 in the back. figure 14 shows the basic sequence layout to be used during the effective pixel readout. the 48 ob pixels at the end of each line are used for the clpob signals. pblk is optional and is often used to blank the digital outputs during the noneffective ccd pixels. hblk is used during the vertical shift interval. the hblk, clpob, and pblk parameters are programmed in the v-sequence registers. more elaborate clamping schemes may be used, such as adding in a separate sequence to clamp during the entire shield ob lines. this requires conf guring a separate v-sequence for reading out the ob lines. v h horizontal ccd register effective image area 28 dummy pixels 48 ob pixels 4 ob pixels 10 vertical ob lines 2 vertical ob lines figure 13. example ccd conf guration vertical shift v ert shift ccdin shp shd h1/h3 h2/h hblk pblk clpob optical b lack dummy effective pixels ob optical black hd figure 14. horizontal sequence example rev. 0 obsolete
ad9995 C16 C vertical timing generation the ad9995 provides a very f exible solution for generating vertical ccd timing, and can support multiple ccds and dif- ferent system architectures. the 6-phase vertical transfer clocks v1Cv6 are used to shift each line of pixels into the horizontal output register of the ccd. the ad9995 allows these outputs to be individually programmed into various readout conf gurations using a 4-step process. figure 15 shows an overview of how the vertical timing is gener- ated in four steps. first, the individual pulse patterns for v1Cv6 are created by using the vertical pattern group registers. second, the v-pattern groups are used to build the sequences, where additional information is added. third, the readout for an entire f eld is constructed by dividing the f eld into different regions and then assigning a sequence to each region. each f eld can contain up to seven different regions to accommodate different steps of the readout such as high speed line shifts and unique vertical line transfers. up to six different f elds may be created. finally, the mode register allows the different f elds to be combined into any order for various readout conf gurations. region 0: use v-sequence 3 region 1: use v-sequence 2 region 2: use v-sequence 1 region 0: use v-sequence 3 region 1: use v-sequence 2 region 2: use v-sequence 1 region 0: use v-sequence 2 region 1: use v-sequence 0 region 3: use v-sequence 0 region 4: use v-sequence 2 create the vertical pattern groups (maximum of 10 groups). build the v-sequences by adding line start position, # of repeats, and hblk/clpob pulses (maximum of 10 v-sequences). v-sequence 0 (vpat0, 1 rep) build each field by dividing into different regions, and assigning a different v-sequence to each (maximum of 7 regions in each field) (maximum of 6 fields). v1 v2 v5 v6 v1 v2 v3 v4 field 0 field 1 field 2 region 2: use v-sequence 3 use the mode register to control which fields are used, and in what order (maximum of 7 fields may be combined in any order). field 0 field 1 field 2 field 3 field 4 field 5 field 1 field 4 field 2 v4 v3 v5 v6 v-sequence 1 (vpat9, 2 rep) v-sequence 2 (vpat9, n rep) vpat 0 v1 v2 v5 v6 v4 v3 v1 v2 v5 v6 v4 v3 v1 v2 v5 v6 v4 v3 vpat 9 figure 15. summary of vertical timing generation rev. 0 obsolete
ad9995 C17 C table v. vertical pattern group registers register length range description vpol 1b high/low starting polarity of each v1Cv6 output vtog1 12b 0C4096 pixel location first toggle position within line for each v1Cv6 output vtog2 12b 0C4096 pixel location second toggle position within line for each v1Cv6 output vtog3 12b 0C4096 pixel location third toggle position within line for each v1Cv6 output vtog4 12b 0C4096 pixel location fourth toggle position, only available in v-pattern groups 8 and 9 vpatlen 12b 0C4096 pixels total length of each v-pattern group freeze1 12b 0C4096 pixel location holds the v1Cv6 outputs at their current levels (static dc) resume1 12b 0C4096 pixel location resumes operation of the v1Cv6 outputs to finish their pattern freeze2 12b 0C4096 pixel location holds the v1Cv6 outputs at their current levels (static dc) resume2 12b 0C4096 pixel location resumes operation of the v1Cv6 outputs to finish their pattern hd v1 programmable settings for each v-pattern: 1. start polarit y 2. first toggle position 3. second toggle position (3rd toggle position also available, 4th toggle position available for v-pattern groups 8 and 9) 4. total pattern length for all v1-v6 outputs start position of v-pattern group is programmable in v-sequence register s 4 1 2 3 v2 1 2 3 v6 1 2 3 figure 16. vertical pattern group programmability vertical pattern groups (vpat) the vertical pattern groups def ne the individual pulse patterns for each v1Cv6 output signal. table v summarizes the registers available for generating each of the 10 v-pattern groups. the start polarity (vpol) determines the starting polarity of the vertical sequence, and can be programmed high or low for each v1Cv6 output. the f rst, second, and third toggle position (vtog1, vtog2, vtog3) are the pixel locations within the line where the pulse transitions. a fourth toggle position (vtog4) is also available for v-pattern groups 8 and 9. all toggle positions are 12-bit values, allowing their placement anywhere in the hori- zontal line. a separate register, vpatstart, specif es the start position of the v-pattern group within the line (see the vertical sequences section). the vpatlen register designates the total length of the v-pattern group, which will determine the number of pixels between each of the pattern repetitions, when repetitions are used (see the vertical sequences section). the freeze and resume registers are used to temporarily stop the operation of the v1Cv6 outputs. at the pixel location specif ed in the freeze register, the v1Cv6 outputs will be held static at their current dc state, high or low. the v1Cv6 outputs are held until the pixel location specif ed by resume register. two sets of freeze/resume registers are pro- vided, allowing the vertical outputs to be interrupted twice in the same line. the freeze and resume positions are pro- grammed in the v-pattern group registers, but are separately enabled using the vmask registers, which are described in the vertical sequence section. rev. 0 obsolete
ad9995 C18 C vertical sequences (vseq) the vertical sequences are created by selecting one of the 10 v-pattern groups and adding repeats, start position, and hori- zontal clamping and blanking information. up to 10 v-sequences can be programmed, each using the registers shown in table vi. figure 17 shows how the different registers are used to generate each v-sequence. the vpatsel register selects which v-pattern group will be used in a given v-sequence. the basic v-pattern group can have repetitions added, for high speed line shifts or line binning, by using the vpatrepo and vpatrepe registers. generally, the same number of repetitions are programmed into both registers, but if a different number of repetitions is required on odd and even lines, separate values may be used for each register (see the v-sequence line alternation section). the vpatstart register specif es where in the line the v-pattern group will start. the vmask register is used in conjunction with the freeze/ resume registers to enable optional masking of the v-outputs. either or both of the freeze1/resume1 and freeze2/ resume2 registers can be enabled. the line length (in pixels) is programmable using the hdlen registers. each v-sequence can have a different line length to accommodate various image readout techniques. the maximum number of pixels per line is 4096. note that the last line of the f eld is separately programmable using the hdlast register located in the field register section. table vi. v-sequence registers (see tables iii and iv for hblk, clpob, pblk registers) register length range description vpatsel 4b 0C9 v-pattern group # selected v-pattern group for each v-sequence. vmask 2b 0C3 mask mode enables the masking of v1Cv6 outputs at the locations specif ed by the freeze/resume registers. 0 = no mask, 1 = enable freeze1/resume1, 2 = enable freeze2/resume2, 3 = enable both 1 and 2. vpatrepo 12b 0C4095 # of repeats number of repetitions for the v-pattern group for odd lines. if no odd/even alternation is required, set to vpatrepe. vpatrepe 12b 0C4095 # of repeats number of repetitions for the v-pattern group for even lines. if no odd/even alternation is required, set to vpatrepo. vpatstart 12b 0C4095 pixel location start position for the selected v-pattern group. hdlen 12b 0C4095 # of pixels hd line length for lines in each v-sequence. vpat rep 3 hd v1Cv 6 programmable settings for each v-sequence : 1. start position in the line of selected v-pattern group 2. hd line lengt h 3. v-pattern select (vpatsel) to select any v-pattern group 4. number of repetitions of the v-pattern group (if needed ) 5. start polarity and toggle positions for clpob and pblk signal s 6. masking polarity and toggle positions for hblk signal v- pattern group 1 3 clpo b pblk hbl k 2 4 4 vpat rep 2 5 6 figure 17. v-sequence programmability rev. 0 obsolete
ad9995 C19 C complete field: combining v-sequences after the v-sequences have been created, they are combined to create different readout f elds. a f eld consists of up to seven different regions, and within each region a different v-sequence can be selected. figure 18 shows how the sequence change posi- tions (scp) designate the line boundary for each region, and the vseqsel registers then select which v-sequence is used during each region. registers to control the vsg outputs are also included in the field registers. table vii summarizes the registers used to create the different f elds. up to six different f elds can be preprogrammed using all of the field registers. the veqsel registers, one for each region, select which of the 10 v-sequences will be active during each region. the sweep registers are used to enable sweep mode during any region. the multi registers are used to enable multiplier mode dur- ing any region. the scp registers create the line boundaries for each region. the vdlen register specif es the total number of lines in the f eld. the total number of pixels per line (hdlen) is specif ed in the v-sequence registers, but the hdlast register specif es the number of pixels in the last line of the f eld. the vpatsecond register is used to add a second v-pattern group to the v1C6 outputs during the sensor gate (vsg) line. the sgmask register is used to enable or disable each indi- vidual vsg output. there is a single bit for each vsg output; setting the bit high will mask the output, setting it low will enable the output. the sgpat register assigns one of the four different sg patterns to each vsg output. the individual sg patterns are created separately using the sg pattern registers. the sgline1 register specif es which line in the f eld will contain the vsg out- puts. the optional sgline2 register allows the same vsg pulses to be repeated on a different line. table vii. field registers register length range description vseqsel 4b 0C9 v-sequence # selected v-sequence for each region in the field. sweep 1b high/low enables sweep mode for each region, when set high. multi 1b high/low enables multiplier mode for each region, when set high. scp 12b 0C4095 line # sequence change position for each region. vdlen 12b 0C4095 # of lines total number of lines in each field. hdlast 12b 0C4095 # of pixels length in pixels of the last hd line in each field. vpatsecond 4b 0C9 v-pattern group # selected v-pattern group for second pattern applied during vsg line. sgmask 6b high/low, each vsg set high to mask each individual vsg output. vsg1 [0], vsg2 [1], vsg3 [2], vsg4 [3], vsg5 [4]. sgpatsel 12b 0C3 pattern #, each vsg selects the vsg pattern number for each vsg output. vsg1 [1:0], vsg2 [3:2], vsg3 [5:4], vsg4 [7:6], vsg5 [9:8]. sgline1 12b 0C4095 line # selects the line in the field where the vsg are active. sgline2 12b 0C4095 line # selects a second line in the field to repeat the vsg signals. vd region 0 field settings : 1. sequence change positions (scp1C6) define each of the 7 regions in the field . 2. vseqsel0C6 selects the desired v-sequence (0C9) for each regi on. 3. sgline1 register selects which hd line in the field will cont ain the sensor gate pulse(s) . v1Cv 6 hd scp 1 scp 2 vseqsel0 vseqsel1 vseqsel1 vseqsel1 vseqsel1 scp 3 vseqsel2 scp 4 vseqsel3 scp 5 vseqsel4 scp 6 vseqsel5 vseqsel6 region 1 region 2 region 3 region 4 region 5 region 6 vsg sgline sgline sgline sgline 1 figure 18. complete field is divided into regions rev. 0 obsolete
ad9995 C20 C generating line alternation for v-sequence and hblk during low resolution readout, some ccds require a different number of vertical clocks on alternate lines. the ad9995 can support this by using the vpatrepo and vpatrepe regis- ters. this allows a different number of vpat repetitions to be programmed on odd and even lines. note that only the number of repeats can be different in odd and even lines, but the vpat group remains the same. additionally, the hblk signal can also be alternated for odd and even lines. when the hblkalt register is set high, the hblk tog1 and tog2 positions will be used on odd lines and the tog3C tog 6 positions will be used on even lines. this allows the hblk interval to be adjusted on odd and even lines if needed. figure 19 shows an example of vpat repetition alternation and hblk alternation used together. it is also possible to use vpat and hblk alternation separately. second v-pattern group during vsg active line most ccds require additional vertical timing during the sensor gate line. the ad9995 supports the option to output a second v-pattern group for v1Cv6 during the line when the sensor gates vsg1Cvsg5 are active. figure 20 shows a typical vsg line, which includes two separate sets of v-pattern groups for v1Cv6. the v- pattern group at the start of the vsg line is selected in the same manner as the other regions, using the appropriate vseqsel register. the second v-pattern group, unique to the vsg line, is selected using the vpatsecond register, located with the field registers. the start position of the second vpat group uses the vpatlen register from the selected vpat registers. because the vpatlen register is used as the start position and not as the vpat length, it is not possible to program multiple repetitions for the second vpat group. v1 v2 vpatrepo = 2 v6 hd vpatrepe = 5 vpatrepo = 2 notes 1. the number of repeats for the v-pattern group may be alternated on odd and even lines. 2. the hblk toggle positions may be alternated between odd and even lines in order to generate different hblk patterns for odd/even lines. hblk tog1 tog2 tog3 tog4 tog1 tog2 figure 19. odd/even line alternation of vpat repetitions and hblk toggle positions v1 v2 v6 hd vsg 2nd vpat group start position for 2nd vpat group uses vpatlen register figure 20. example of second vpat group during sensor gate line rev. 0 obsolete
ad9995 C21 C sweep mode operation the ad9995 contains an additional mode of vertical timing operation called sweep mode. this mode is used to generate a large number of repetitive pulses that span multiple hd lines. one example of where this mode is needed is at the start of the ccd readout operation. at the end of the image exposure but before the image is transferred by the sensor gate pulses, the vertical interline ccd registers should be free of all charge. this can be accomplished by quickly shifting out any charge using a long series of pulses from the v1Cv6 outputs. depending on the vertical resolution of the ccd, up to 2,000 or 3,000 clock cycles will be needed to shift the charge out of each vertical ccd line. this operation will span across multiple hd line lengths. nor- mally, the ad9995s vertical timing must be contained within one hd line length, but when sweep mode is enabled, the hd boundaries will be ignored until the region is f nished. to enable sweep mode within any region, program the appropriate sweep register to high. figure 21 shows an example of sweep mode operation. the number of vertical pulses needed will depend on the vertical resolution of the ccd. the v1Cv6 output signals are gener- ated using the v-pattern registers (shown in table vii). a single pulse is created using the polarity and toggle position registers. the number of repetitions is then programmed to match the number of vertical shifts required by the ccd. repetitions are programmed in the v-sequence registers using the vpatrep registers. this produces a pulse train of the appropriate length. normally, the pulse train would be truncated at the end of the hd line length, but with sweep mode enabled for this region, the hd boundaries will be ignored. in figure 21, the sweep region occupies 23 hd lines. after the sweep mode region is completed, in the next region, normal sequence operation will resume. when using sweep mode, be sure to set the region boundaries (using the sequence change positions) to the appro- priate lines to prevent the sweep operation from overlapping the next v-sequence. multiplier mode to generate very wide vertical timing pulses, a vertical region may be conf gured into a multiplier region. this mode uses the v-pattern registers in a slightly different manner. multiplier mode can be used to support unusual ccd timing requirements, such as vertical pulses that are wider than a single hd line length. the start polarity and toggle positions are still used in the same manner as the standard vpat group programming, but the vpatlen is used differently. instead of using the pixel counter (hd counter) to specify the toggle position locations (vtog1, 2, 3) of the vpat group, the vpatlen is multiplied with the vtog position to allow very long pulses to be generated. to cal- culate the exact toggle position, counted in pixels after the start position, use the equation multiplier modetoggleposition vtog vpatlen = because the vtog register is multiplied by vpatlen, the resolution of the toggle position placement is reduced. if vpatlen = 4, the toggle position accuracy is now reduced to 4-pixel steps instead of single pixel steps. table viii sum- marizes how the vpat group registers are used in multiplier mode operation. in multiplier mode, the vpatrepo and vpatrepe registers should always be programmed to the same value as the highest toggle position. vd v1Cv 6 hd region 1: sweep region line 0 l 0 l ine 1 region 0 region 2 line 24 line 25 line 2 scp 1 scp 2 fr 21. exmp f sp rn fr h spd vrt sft table viii. multiplier mode register parameters register length range description multi 1b high/low high enables multiplier mode. vpol 1b high/low starting polarity of v1Cv6 signal in each vpat group. vtog1 12b 0C4095 pixel location first toggle position for v1Cv6 signal in each vpat group. vtog2 12b 0C4095 pixel location second toggle position for v1Cv6 signal in each vpat group. vtog3 12b 0C4095 pixel location third toggle position for v1Cv6 signal in each vpat group. vpatlen 10b 0C1023 pixels used as multiplier factor for toggle position counter. vpatrep 12b 0C4096 vpatrepe/vpatrepo should be set to the same value as tog2 or 3. rev. 0 obsolete
ad9995 C22 C the example shown in figure 22 illustrates this operation. the f rst toggle position is 2, and the second toggle position is 9. in non-multiplier mode, this causes the v-sequence to toggle at pixel 2 and then pixel 9 within a single hd line. however, toggle positions are now multiplied by the vtplen = 4, so the f rst toggle occurs at pixel count 8 and the second toggle occurs at pixel count 36. sweep mode has also been enabled to allow the toggle positions to cross the hd line boundaries. vertical sensor gate (shift gate) patterns in an interline ccd, the vertical sensor gates (vsg) are used to transfer the pixel charges from the light-sensitive image area into light-shielded vertical registers. from the light-shield verti- cal registers, the image is then read out line-by-line by using the vertical transfer pulses v1Cv6 in conjunction with the high speed horizontal clocks. table ix contains the summary of the vsg pattern registers. the ad9995 has f ve vsg outputs, vsg1Cvsg5. each of the out- puts can be assigned to one of four programmed patterns by using the sgpatsel registers. each pattern is generated in a similar manner as the v-pattern groups, with a programmable start polar- ity (sgpol), f rst toggle position (sgtog1), and second toggle position (sgtog2). the active line where the vsg1Cvsg5 pulses occur is programmable using the sgline1 and sgline2 registers. additionally, any of the vsg1Cvsg5 pulses may be individually disabled by using the sgmask register. the individ- ual masking allows all of the sg patterns to be preprogrammed, and the appropriate pulses for the different f elds can be separately enabled. for maximum f exibility, the sgpatsel, sgmask, and sgline registers are separately programmable for each f eld. more detail is given in the complete field section. v1Cv 6 hd vpatlen multiplier mode v-pattern group properties: 1. start polarity (above: startpol = 0) 2. first, second, and third toggle positions (above: vtog1 = 2, vto g2 = 9) 3. length of vpat counter (above: vpatlen = 4). this is the minimum resolution for toggle position changes. 4. toggle positions occur at location equal to (vtog vpatlen ) 5. if sweep region is enabled, the v-pulses may also cross the hd boundries, as shown abov e 1 2 1 2 3 4 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 1 2 3 4 3 4 1 2 3 1 2 3 4 1 4 1 2 3 2 3 4 start position of vpat group is still programmed in the v-sequence register s pixel numbe r 1 2 3 4 2 3 4 5 6 7 8 5 6 7 8 9 1 9 1 0 1 0 1 1 1 1 1 2 1 2 1 3 1 3 1 4 1 4 1 5 1 5 1 6 1 6 1 7 1 7 1 8 1 8 1 9 2 9 2 0 2 0 2 1 2 1 2 2 2 2 2 3 2 3 2 4 2 4 2 5 2 5 2 6 2 6 2 7 2 7 2 8 2 8 2 9 3 9 3 0 3 0 3 1 3 1 3 2 3 2 3 3 3 3 3 4 3 4 3 5 3 5 3 6 3 6 3 6 3 6 3 6 3 7 3 7 3 8 3 8 3 9 4 9 4 0 3 5 5 4 1 2 4 2 figure 22. example of multiplier region for wide vertical pulse timing table ix. vsg pattern registers (also see field registers in table vii) register length range description sgpol 1b high/low sensor gate starting polarity for sg pattern 0C3 sgtog1 12b 0C4095 pixel location first toggle position for sg pattern 0C3 sgtog2 12b 0C4095 pixel location second toggle position for sg pattern 0C3 vd hd programmable settings for each pattern: 1. start polarity of pulse 2. first toggle position 3. second toggle position 4. active line for vsg pulses within the field (programmable in the field register, not for each pattern) vsg patterns 4 1 2 3 figure 23. vertical sensor gate pulse placement rev. 0 obsolete
ad9995 C23 C table x. mode register data bit breakdown (d23 = msb) d23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 d0 total number of 7th field 6th field 5th field 4th field 3rd field 2nd field 1st field fields to use. 0 = field 0 0 = field 0 0 = field 0 0 = field 0 0 = field 0 0 = field 0 0 = field 0 1 = 1st field only 5 = field 5 5 = field 5 5 = field 5 5 = field 5 5 = field 5 5 = field 5 5 = field 5 7 = all 7 fields 6, 7 = invalid 6, 7 = invalid 6, 7 = invalid 6, 7 = invalid 6, 7 = invalid 6, 7 = invalid 6, 7 = invalid 0 = invalid example 1: total fields = 3, 1st field = field 0, 2nd field = field 1, 3rd field = field 2 mode register contents = 0x600088 field 0 field 1 field 2 field 3 field 4 field 5 field 1 field 4 field 2 example 2: total fields = 2, 1st field = field 3, 2nd field = field 4 mode register contents = 0x400023 example 3: total fields = 4, 1st field = field 5, 2nd field = field 1, 3rd field = field 4, 4th field = field 2 mode register contents = 0x80050d figure 24. using the mode register to select field timing mode register the mode register is a single register that selects the f eld tim- ing of the ad9995. typically, all of the f eld, v-sequence, and v-pattern group information is programmed into the ad9995 at startup. during operation, the mode register allows the user to select any combination of f eld timing to meet the current requirements of the system. the advantage of using the mode register in conjunction with preprogrammed timing is that it greatly reduces the system programming requirements during camera operation. only a few register writes are required when the camera operating mode is changed, rather than having to write in all of the vertical timing information with each camera mode change. a basic still camera application might require f ve different f elds of vertical timing: one for draft mode operation, one for autofocusing, and three for still image readout. all of the reg- ister timing information for the f ve f elds would be loaded at startup. then, during camera operation, the mode register would select which f eld timing would be active, depending on how the camera was being used. table x shows how the mode register bits are used. the three msbs, d23Cd21, are used to specify how many total f elds will be used. any value from 1 to 7 can be selected using these three bits. the remaining register bits are divided into 3-bit sections to select which of the six f elds are used and in which order. up to seven f elds may be used in a single mode write. the ad9995 will start with the field timing specif ed by the f rst field bits, and on the next vd will switch to the timing specif ed by the second field bits, and so on. after completing the total number of f elds specif ed in bits d23 to d21, the ad9995 will repeat by starting at the f rst field again. this will continue until a new write to the mode register occurs. figure 24 shows example mode register set- tings for different f eld conf gurations. rev. 0 obsolete
ad9995 C24 C vertical timing example to better understand how the ad9995s vertical timing generation is used, consider the example ccd timing chart in figure 25. this particular example illustrates a ccd using a general 3-f eld readout technique. as described in the field section, each readout f eld should be divided into separate regions to per- form each step of the readout. the sequence change positions (scp) determine the line boundaries for each region, and the vseqsel registers will then assign a particular v-sequence to each region. the v-sequences will contain the specif c timing information required in each region: v1Cv6 pulses (using vpat groups), hblk/clpob timing, and vsg patterns for the sg active lines. this particular timing example requires four regions for each of the three f elds, labeled region 0, region 1, region 2, and region 3. because the ad9995 allows up to six individual f elds to be programmed, the field 0, field 1, and field 2 registers can be used to meet the requirements of this timing example. the four regions for each f eld are very similar in this example, but the individual registers for each f eld allow f exibility to accom- modate other timing charts. region 0 is a high speed vertical shift region. sweep mode can be used to generate this timing operation, with the desired number of high speed vertical pulses needed to clear any charge from the ccds vertical registers. region 1 consists of only two lines, and uses standard single line vertical shift timing. the timing of this region area will be the same as the timing in region 3. region 2 is the sensor gate line, where the vsg pulses transfer the image into the vertical ccd registers. this region may require the use of the second v-pattern group for sg active line. region 3 also uses the standard single line vertical shift timing, the same timing as region 1. in summary, four regions are required in each of the three f elds. the timing for regions 1 and 3 is essentially the same, reducing the complexity of the register programming. other registers will need to be used during the actual readout operation, such as the mode register, shutter control registers (trigger, subck, vsub, mshut, strobe), and afe gain register. these registers will be explained in other examples. important note about signal polarities when programming the ad9995 to generate the v1Cv6, vsg1Cvsg5, and subck signals, it is important to note that the v-driver circuit usually inverts these signals. carefully check the required timing signals needed at the input and output of the v-driver circuit being used and adjust the polarities of the ad9995s outputs accordingly. rev. 0 obsolete
ad9995 C25 C vd hd v1 v2 v5 v6 subck mshut vsub ccd out exposure ( t exp ) first field readout region 1 region 2 region 0 region 3 1 4 7 10 13 16 nC5 nC2 closed 2 5 8 11 14 17 20 nC4 nC1 open v3 v4 open 3 6 9 12 15 18 21 n region 1 region 2 region 0 region 3 region 1 region 2 region 0 region 3 second field readout third field readout field 0 field 1 field 2 nC 3 figure 25. ccd timing example: dividing each field into regions rev. 0 obsolete
ad9995 C26 C shutter timing control the ccd image exposure time is controlled by the substrate clock signal (subck), which pulses the ccd substrate to clear out accumulated charge. the ad9995 supports three types of electronic shuttering: normal shutter, high precision shutter, and low speed shutter. along with the subck pulse placement, the ad9995 can accommodate different readout conf gurations to further suppress the subck pulses during multiple f eld readouts. the ad9995 also provides programmable outputs to control an external mechanical shutter (mshut), strobe/f ash (strobe), and the ccd bias select signal (vsub). normal shutter operation by default, the ad9995 is always operating in the normal shutter conf guration in which the subck signal is pulsing in every vd f eld (see figure 26). the subck pulse occurs once per line, and the total number of repetitions within the f eld will determine the length of the exposure time. the subck pulse polarity and toggle positions within a line are programmable using the subckpol and subck1tog registers (see table xi). the number of subck pulses per f eld is programmed in the subcknum register (addr. 0x63). as shown in figure 26, the subck pulses will always begin in the line following the sg active line, which is specif ed in the sgactline registers for each f eld. the subckpol, subck1tog, subck2tog, subcknum, and subck- suppress registers are updated at the start of the line after the sensor gate line, as described in the updating new register values section. high precision shutter operation high precision shuttering is used in the same manner as nor- mal shuttering, but uses an additional register to control the very last subck pulse. in this mode, the subck still pulses once per line, but the last subck in the f eld will have an additional subck pulse whose location is determined by the subck2tog register, as shown in figure 27. finer resolution of the exposure time is possible using this mode. leaving the subck2tog register set to max value (0xffffff) will disable the last subck pulse (default setting). low speed shutter operation normal and high precision shutter operations are used when the exposure time is less than one f eld long. for long exposure times greater than one f eld interval, low speed shutter opera- tion is used. the ad9995 uses a separate exposure counter to achieve long exposure times. the number of f elds for the low speed shutter operation is specif ed in the exposure register (addr. 0x62). as shown in figure 28, this shutter mode will suppress the subck and vsg outputs for up to 4095 f elds (vd periods). the vd and hd outputs may be suppressed during the exposure period by programming the vdhdoff register to 1. to generate a low speed shutter operation, it is necessary to trig- ger the start of the long exposure by writing to the trigger register bit d3. when this bit is set high, the ad9995 will begin an exposure operation at the next vd edge. if a value greater than zero is specif ed in the exposure register, the ad9995 will suppress the subck output on subsequent f elds. vd subck subck programmable settings: 1. pulse polarity using the subckpol register. 2. number of pulses within the field using the subcknum register (subcknum = 3 in the above figure). 3. pixel location of pulse within the line and pulsewidth prog rammed using subck1 toggle position register. t exp vsg hd t exp figure 26. normal shutter mode vd subck notes 1. second subck pulse is added in the last subck line. 2. location of 2nd pulse is fully programmable using the subck2 toggle position register. vsg hd t exp t exp figure 27. high precision shutter mode rev. 0 obsolete
ad9995 C27 C if the exposure is generated using the trigger register and the exposure register is set to zero, the behavior of the subck will not be any different than the normal shutter or high precision shutter operations, in which the trigger register is not used. subck suppression normally, the subcks will begin to pulse on the line following the sensor gate line (vsg). with some ccds, the subck pulse needs to be suppressed for one or more lines following the vsg line. the subcksuppress register allows for suppression of the subck pulses for additional lines following the vsg line. readout after exposure after the exposure, the readout of the ccd data occurs, beginning with the sensor gate (vsg) operation. by default, the ad9995 is generating the vsg pulses in every f eld. in the case where only a single exposure and single readout frame are needed, such as the ccds preview mode, the vsg and subck pulses can be oper- ating in every f eld. however in many cases, during readout the subck output needs to be further suppressed until the readout is completed. the readout register specif es the number of additional f elds after the exposure to continue the suppression of subck. readout can be programmed for zero to seven additional f elds, and should be preprogrammed at startup, not at the same time as the exposure write. a typical interlaced ccd frame read out mode will generally require two additional f elds of subck suppression (readout = 2). a 3-f eld, 6-phase ccd will require three additional f elds of subck sup- pression after the readout begins (readout = 3). if the subck output is required to start back up during the last f eld of readout, simply program the readout register to one less than the total number of ccd readout f elds. like the exposure operation, the readout operation must be trig- gered by using the trigger register. using the trigger register as described previously, by default the ad9995 will output the subck and vsg signals on every f eld. this works well for continuous single f eld exposure and readout operations, such as the ccds live preview mode. however, if the ccd requires a longer exposure time, or if multiple readout f elds are needed, the trigger register is needed to initiate specif c exposure and readout sequences. typically, the exposure and readout bits in the trigger register are used together. this will initiate a complete exposure- plus-readout operation. once the exposure has been completed, the readout will automatically occur. the values in the expo- sure and readout registers will determine the length of each operation. vd subck notes 1. subck may be suppressed for multiple fields by programming the exposure register greater than zero. 2. above example uses exposure = 1. 3. trigger register must also be used to start the low speed exp osure . 4. vd/hd outputs may also be suppressed using the vdhdoff register = 1. t exp vsg trigge r exposure figure 28. low speed shutter mode using exposure register table xi. shutter mode register parameters register length range description trigger 5b on/off for five signals trigger for vsub [0], mshut [1], strobe [2], exposure [3], and readout start [4] readout 3b 0C7 # of fields number of fields to suppress subck after exposure exposure 12b 0C4095 # of fields number of fields to suppress to subck and vsg during exposure time (low speed shutter) vdhdoff 1b on/off disable vd/hd output during exposure (1 = on, 0 = off) subckpol * 1b high/low subck start polarity for subck1 and subck2 subck1tog * 24b 0C4095 pixel locations toggle positions for first subck pulse (normal shutter) subck2tog * 24b 0C4095 pixel locations toggle positions for second subck pulse in last line (high precision) subcknum * 12b 1C4095 # of pulses total number of subcks per field at one pulse per line subcksuppress * 12b 0C4095 # of pulses number of lines to further suppress subck after the vsg line * register is not vd updated, but is updated at the start of line after sensor gate line. rev. 0 obsolete
ad9995 C28 C it is possible to independently trigger the readout operation without triggering the exposure operation. this will cause the readout to occur at the next vd, and the subck output will be suppressed according to the value of the readout register. the trigger register is also used to control the strobe, mshut, and vsub signal transitions. each of these signals are individually controlled, although they will be dependent on the triggering of the exposure and readout operation. see figure 32 for a complete example of triggering the exposure and readout operations. vsub control the ccd readout bias (vsub) can be programmed to accom- modate different ccds. figure 29 shows two different modes that are available. in mode 0, vsub goes active during the f eld of the last subck when the exposure begins. the on position (rising edge in figure 29) is programmable to any line within the f eld. vsub will remain active until the end of the image readout. in mode 1, the vsub is not activated until the start of the readout. an additional function called vsub keep-on is also available. when this bit is set high, the vsub output will remain on (active) even after the readout has f nished. to disable the vsub at a later time, set this bit back to low. mshut and strobe control mshut and strobe operation is shown in figures 30, 31, and 32. table xii shows the register parameters for controlling the mshut and strobe outputs. the mshut output is switched on with the mshuton registers, and will remain on until the location specif ed in the mshutoff registers. the location of mshutoff is fully programmable to anywhere within the exposure period, using the fd (f eld), ln (line), and px (pixel) registers. the strobe pulse is def ned by the on and vd subck vsub operation: 1. active polarity is polarity (above example is vsub active high) . 2. on position is programmable. mode 0 turns on at the start of exposure, mode 1 turns on at the start of readout. 3. off position occurs at end of readout. 4. optional vsub keep-on mode will leave the vsub active at the end of readout. t exp vsg1 vsub 3 1 2 readout 2 4 mode 0 mode 1 trigger vsub figure 29. vsub programmability vd subck mshut programmable settings: 1. active polarity. 2. on position is vd updated and may be switched on at any time. 3. off position can be programmed anywhere from the field of la st subck until the field before readout. t exp vsg mshut 3 1 2 trigger exposure and mshut figure 30. mshut output programmability rev. 0 obsolete
ad9995 C29 C off positions. strobon_fd is the f eld in which the strobe is turned on, measured from the f eld containing the last subck before exposure begins. the strobon_ ln px register gives the line and pixel positions with respect to strobon_fd. the strobe off position is programmable to any f eld, line, and pixel location with respect to the f eld of the last subck. trigger register limitations while the trigger register can be used to perform a complete exposure and readout operation, there are limitations on its use. once an exposure-plus-readout operation has been triggered, another exposure/readout operation cannot be triggered right away. there must be at least one idle f eld (vd intervals) before the next exposure/readout can be triggered. the same limitation applies to the triggering of the mshut signal. there must be at least one idle f eld after the completion of the mshut off operation before another mshut off operation may be programmed. the vsub trigger requires two idle f elds between exposure/ readout operations in order to ensure proper vsub on/off trig- gering. if the vsub signal is not required to be turned on and off in between each successive exposure/readout operation, this limitation can be ignored. the vsub keep-on mode is useful when successive exposure/readout operations are required. vd subck strobe programmable settings : 1. active polarity. 2. on position is programmable in any field during the exposure time (with respect to the field containing the last subck). 3. off position is programmable in any field during the exposure time. t exp vsg strobe 1 2 3 trigge r exposure and strobe figure 31. strobe output programmability table xii. vsub, mshut, and strobe register parameters register length range description vsubmode[0] 1b high/low vsub mode (0 = mode 0, 1 = mode 1) (see figure 29). vsubmode[1] 1b high/low vsub keep-on mode. vsub will stay active after readout when set high. vsubon[11:0] 12b 0C4095 line location vsub on position. active starting in any line of f eld. vsubon[12] 1b high/low vsub active polarity. mshutpol[0] 1b high/low mshut active polarity. mshutpol[1] 1b on/off mshut manual enable (1 = active or open). mshuton 24b 0C4095 line/pix location mshut on position line [11:0] and pixel [23:12] location. mshutoff_fd 12b 0C4095 field location field location to switch off mshut (inactive or closed). mshutoff_lnpx 24b 0C4095 line/pix location line/pixel position to switch off mshut (inactive or closed). strobpol 1b high/low strobe active polarity. strobon_fd 12b 0C4095 field location strobe on field location, with respect to last subck field. strobon_lnpx 24b 0C4095 line/pix location strobe on line/pixel position. stroboff_fd 12b 0C4095 field location strobe off field location, with respect to last subck field. stroboff_lnpx 24b 0C4095 line/pix location strobe off line/pixel position. rev. 0 obsolete
ad9995 C30C ad9995 C31C draft image serial writes vd vsg subck strobe mshut mechanical shutter vsub ccd out 1 9 10 8 7 6 2 t exp 4 5 3 open closed mode 0 mode 1 10 10 10 open still image 3rd field still image 2nd field still image 1st field draft image draft image still image readout figure 32. example of exposure and still image readout using shutter signals and mode register 1. write to the readout register (addr. 0x61) to specify the number of felds to further suppress subck while the ccd data is read out. in this example, readout = 3. write to the exposure register (addr. 0x62) to specify the number of felds to suppress subck and vsg outputs during exposure. in this example, exposure = 1. write to the trigger register (addr. 0x60) to enable the strobe, mshut, and vsub signals, and to start the exposure/readout operation. to trigger all of these events (as in figure 32), set the register trigger = 31. readout will automatically occur after the exposure period is fnished. write to the mode register (addr. 0x1b) to confgure the next fve felds. the frst two felds during exposure are the same as the current draft mode felds, and the following three felds are the still frame readout felds. the registers for the draft mode feld and the three readout felds have already been programmed. 2. vd/hd falling edge will update the serial writes from 1. 3. if vsub mode = 0 (addr. 0x67), vsub output turns on at the line specifed in the vsubon register (addr. 0x68). 4. strobe output turns on and off at the location specifed in the strobeon and off registers (addr. 0x6e to addr. 0x71). 5. mshut output turns off at the location specifed in the mshutoff registers (addr. 0x6b and 0x6c). 6. the next vd falling edge will automatically start the frst readout feld. 7. the next vd falling edge will automatically start the second readout feld. 8. the next vd falling edge will automatically start the third readout feld. 9. write to the mode register to reconfgure the single draft mode feld timing. write to the mshuton register (addr. 0x6a) to open the mechanical shutter. 10. vd/hd falling edge will update the serial write from 9. vsg outputs return to draft mode timing. subck output resumes operation. mshut output returns to the on position (active or open). vsub output returns to the off position (inactive). exposure and readout example rev. 0 rev. 0 obsolete
ad9995 C30C ad9995 C31C 6dbC42db ccdin digital filter clpob dc restore optical bla ck clamp 12-bit adc v ga d ac clamp level register 8 v ga gain register cds internal v ref 2v full scale 1 2 precision timing generation shp shd 1.5v output d ata latch reft refb dout phase v -h timing generation shp shd dout phase clpob pblk pblk 1.0v 2.0v dout ad9995 1.0f 1.0f 0.1f figure 33. analog front end functional block diagram analog front end description and operation the ad9995 signal processing chain is shown in figure 33. each processing step is essential in achieving a high quality image from the raw ccd pixel data. dc restore to reduce the large dc offset of the ccd output signal, a dc restore circuit is used with an external 0.1 f series coupling capacitor. this restores the dc level of the ccd signal to approximately 1.5 v, to be compatible with the 3 v supply voltage of the ad9995. correlated double sampler the cds circuit samples each ccd pixel twice to extract the video information and reject low frequency noise. the timing shown in figure 7 illustrates how the two internally generated cds clocks, shp and shd, are used to sample the reference level and level of the ccd signal, respectively. the placement of the shp and shd sampling edges is determined by the setting of the sampcontrol register located at addr. 0x63. place - ment of these two clock signals is critical in achieving the best performance from the ccd. variable gain amplifer the vga stage provides a gain range of 6 db to 42 db, program - mable with 10-bit resolution through the serial digital interface. the minimum gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. when compared to 1 v full-scale systems, the equivalent gain range is 0 db to 36 db. the vga gain curve follows a linear-in-db characteristic. the exact vga gain can be calculated for any gain register value by using the equation gain db code db ( ) ( ) = + 0 0351 6 . where the code range is 0 to 1023. vga gain register code 42 0 vga gain (db) 127 255 383 511 639 767 895 1023 36 30 24 18 12 6 figure 34. vga gain curve rev. 0 rev. 0 obsolete
ad9995 C32C ad9995 C33C a/d converter the ad9995 uses a high performance adc architecture op timized for high speed and low power. differential nonlinearity (dnl) performance is typically better than 0.5 lsb. the adc uses a 2 v input range. see tpc 2 and tpc 3 for typical linearity and noise performance plots for the ad9995. optical black clamp the optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the ccds black level. during the optical black (shielded) pixel inter - val on each line, the adc output is compared with a fxed black level reference, selected by the user in the clamp level register. the value can be programmed between 0 lsb and 255 lsb in 256 steps. the resulting error signal is fltered to reduce noise, and the correction value is applied to the adc input through a d/a converter. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamp - ing is used during the postprocessing, the ad9995 optical black clamping may be disabled using bit d2 in the oprmode regis - ter. when the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment. the clpob pulse should be placed during the ccds optical black pixels. it is recommended that the clpob pulse dura - tion be at least 20 pixels wide to minimize clamp noise. shorter pulsewidths may be used, but clamp noise may increase, and the ability to track low frequency variations in the black level will be reduced. see the horizontal clamping and blanking section and the horizontal timing sequence example section for timing examples. digital data outputs the ad9995 digital output data is latched using the dout phase register value, as shown in figure 33. output data timing is shown in figure 8a. it is also possible to leave the output latches transparent so that the data outputs are valid immediately from the a/d converter. programming the afe control register bit d4 to 1 will set the output latches transparent. the data outputs can also be disabled (three-stated) by setting the afe control register bit d3 to 1. the data output coding is normally straight binary, but the coding my be changed to gray coding by setting the afe con - trol register bit d5 to 1. rev. 0 rev. 0 obsolete
ad9995 C32C ad9995 C33C t pwr 2 1 3 4 5 6 7 8 9 10 11 12 t sync 1v 1st field 1h clocks active when out control register is updated at vd/hd edge h2/h4 h1/h3, rg, dclk digital outputs hd (output) vd (output) sync (input) serial writes cli (input) vdd (input) figure 35. recommended power-up sequence and synchronization, master mode power-up and synchronization recommended power-up sequence for master mode when the ad9995 is powered up, the following sequence is recommended (refer to figure 35 for each step). note that a sync signal is required for master mode operation. if an exter - nal sync pulse is not available, it is also possible generate an internal sync pulse by writing to the syncpol register, as described in the next section. 1. turn on power supplies for ad9995. 2. apply the master clock input cli. 3. reset the internal ad9995 registers by writing a 1 to the sw_reset register (addr. 0x10 in bank 1). 4. by default, the ad9995 is in standby3 mode. to place the part into normal power operation, write 0x004 to the afe oprmode register (addr. 0x00 in bank 1). 5. write a 1 to the bankselect register (addr. 0x7f). this will select register bank 2. 6. load bank 2 registers with the required vpat group, v-sequence, and feld timing information. 7. write a 0 to the bankselect register to select bank 1. 8. by default, the internal timing core is held in a reset state with tgcore_rstb register = 0. write a 1 to the tg - core_rstb register (addr. 0x15 in bank 1) to start the internal timing core operation. 9. load the required registers to confgure the high speed tim - ing, horizontal timing, and shutter timing information. 10. confgure the ad9995 for master mode timing by writing a 1 to the master register (addr. 0x20 in bank 1). 11. w rite a 1 to the out_control register (addr. 0x11 in bank 1). this will allow the outputs to become active after the next sync rising edge. 12. generate a sync event: if sync is high at power-up, bring the sync input low for a minimum of 100 ns. then bring sync back high. this will cause the internal counters to reset and will start vd/hd operation. the frst vd/hd edge allows most bank 1 register updates to occur, including out_control to enable all outputs. table xiii. power-up register write sequence address data description 0x10 0x01 reset all registers to default values 0x00 0x04 power up the afe and clo oscillator 0x7f 0x01 select register bank 2 0x00C0xff vpat, v-sequence, and field timing 0x7f 0x00 select register bank 1 0x15 0x01 reset internal timing core 0x30C71 horizontal and shutter timing 0x20 0x01 confgure for master mode 0x11 0x01 enable all outputs after sync 0x13 0x01 syncpol (for software sync only) generating software sync without external sync signal if an external sync pulse is not available, it is possible to generate an internal sync in the ad9995 by writing to the syncpol register (addr. 0x13). if the software sync option is used, the sync input (pin 46) should be tied to ground (vss). after power-up, follow the same procedure as before for steps 1 to 11. then, for step 12, instead of using the external sync pulse, write a 1 to the syncpol register. this will generate the sync internally, and timing operation will begin. rev. 0 rev. 0 obsolete
ad9995 C34 C vd hd notes 1. sync rising edge resets vd/hd and counters to zero. 2. sync polarity is programmable using syncpol register (addr 0x13). 3. during sync low, all internal counters are reset and vd/hd can be suspended using the syncsuspend register (addr 0x14). 4. if syncsuspend = 1, vertical clocks, h1Ch2, and rg are held at their default polarities. 5. if syncsuspend = 0, all clock outputs continue to operate normall y until sync reset edge. suspend sync h124, rg, v1Cv4, vsg, subck figure 36. sync timing to synchronize ad9995 with external timing 0 1 2 3 4 5 6 7 8 h-counter reset vd notes internal h-counter is reset 17 cli cycles after the hd falli ng edge (when using vdhdpol = 0). typical timing relationship: cli rising edge is coincident wi th hd falling edge. hd cli x xx x x xx xx h-counter (pixel counter) x xx x x x xx xx 9 figure 37. external vd/hd and internal h-counter synchronization, slave mode sync during master mode operation the sync input may be used at any time during operation to resync the ad9995 counters with external timing, as shown in figure 36. the operation of the digital outputs may be suspended during the sync operation by setting the syncsuspend register (addr. 0x14) to 1. power-up and synchronization in slave mode the power-up procedure for slave mode operation is the same as the procedure described for master mode operation, with two exceptions: ? eliminate step 9. do not write the part into master mode. ? no sync pulse is required in slave mode. substitute step 12 with starting the external vd and hd signals. this will syn- chronize the part, allow bank 1 register updates, and start the timing operation. when the ad9995 is used in slave mode, the vd and hd inputs are used to synchronize the internal counters. following a falling edge of vd, there will be a latency of 17 master clock cycles (cli) after the falling edge of hd until the internal h-counter will be reset. the reset operation is shown in figure 37. standby mode operation the ad9995 contains three different standby modes to optimize the overall power dissipation in a particular application. bits [1:0] of the oprmode register control the power-down state of the device: oprmode [1:0] = 00 = normal operation (full power) oprmode[1:0] = 01 = standby 1 mode oprmode[1:0] = 10 = standby 2 mode oprmode[1:0] = 11 = standby 3 mode (lowest overall power) table xiv summarizes the operation of each power-down mode. note that the out_control register takes priority over the standby 1 and standby 2 modes in determining the digital output states, but standby 3 mode takes priority over out_control. standby 3 has the lowest power consumption, and even shuts down the crystal oscillator cir- cuit between cli and clo. therefore, if cli and clo are being used with a crystal to generate the master clock, this circuit will be powered down and there will be no clock signal. when returning from standby 3 mode to normal operation, the timing core must be reset at least 500 s after the oprmode register is written to. this will allow suff cient time for the crys- tal circuit to settle. rev. 0 obsolete
ad9995 C35 C table xiv. standby mode operation i/o block standby 3 (default) 1, 2 out _cont = lo 2, 3 standby 2 3, 4 standby 1 3, 4 afe off no change off only reft, refb on timing core off no change off on clo oscillator off no change on on clo hi running running running v1 lo lo lo lo v2 lo lo lo lo v3 lo lo lo lo v4 lo lo lo lo v5 lo hi hi hi v6 lo hi hi hi vsg1 lo hi hi hi vsg2 lo hi hi hi vsg3 lo hi hi hi vsg4 lo hi hi hi vsg5 lo hi hi hi subck lo hi hi hi vsub lo lo lo lo mshut lo lo lo lo strobe lo lo lo lo h1 hi-z lo lo (4.3 ma) lo (4.3 ma) h2 hi-z hi hi (4.3 ma) hi (4.3 ma) h3 hi-z lo lo (4.3 ma) lo (4.3 ma) h4 hi-z hi hi (4.3 ma) hi (4.3 ma) rg hi-z lo lo (4.3 ma) lo (4.3 ma) vd lo vdhdpol value vdhdpol value vdhdpol vdhdpol value vdhdpol value vdhdpol running hd lo vdhdpol value vdhdpol value vdhdpol vdhdpol value running dclk lo lo lo running dout lo lo lo lo notes 1 to exit standby 3, f rst write 00 to oprmode[1:0], then reset the timing core after ~500 s to guarantee proper settling of the oscillator. 2 standby 3 mode takes priority over out_control for determining the output polarities. 3 these polarities assume out_cont = hi because out_control = lo takes priority over standby 1 and 2. 4 standby 1 and 2 will set h and rg drive strength to minimum value (4.3 ma). rev. 0 obsolete
ad9995 C36C ad9995 C37C circuit layout information the ad9995 typical circuit connection is shown in figure 38. the pcb layout is critical in achieving good image quality from the ad999x products. all of the supply pins, particularly the avdd1, tcvdd, rgvdd, and hvdd supplies, must be decoupled to ground with good quality, high frequency chip ca pacitors. the decoupling capacitors should be located as close as possible to the supply pins and should have a very low impedance path to a continuous ground plane. there should also be a 4.7 f or larger value bypass capacitor for each main supplyavdd, rgvdd, hvdd, and drvddalthough this is not necessary for each individual pin. in most applica tions, it is easier to share the supply for rgvdd and hvdd, which may be done as long as the individual supply pins are separately bypassed. a separate 3 v supply may also be used for drvdd, but this supply pin should still be decoupled to the same ground plane as the rest of the chip. a separate ground for drvss is not recommended. it is recommended that the exposed paddle on the bottom of the package be soldered to a large pad, with multiple vias connecting the pad to the ground plane. the analog bypass pins (reft, refb) should also be carefully decoupled to ground as close as possible to their respective pins. the analog input (ccdin) capacitor should also be located close to the pin. the h1Ch4 and rg traces should be designed to have low inductance to avoid excessive distortion of the signals. heavier traces are recommended because of the large transient cur- rent demand on h1Ch4 by the ccd. if possible, locating the ad9995 physically closer to the ccd will reduce the inductance on these lines. as always, the routing path should be as direct as possible from the ad9995 to the ccd. the ad9995 also contains an on-chip oscillator for driving an external crystal. figure 39 shows an example application using a typical 24 mhz crystal. for the exact values of the external resistors and capacitors, it is best to consult with the crystal manufacturers data sheet. 20pf d10 35 20pf cli clo ad9995 24mhz xtal 34 1m 500m figure 39. crystal driver application output from ccd 12 data outputs line/field/dclk to asic/dsp 3v analog supply external sync from asic/dsp 3 3 serial interface to asic or dsp to strobe circuit to mechanical shutter circuit 3v analog supply 3v rg supply 3v h1Ch4 supply 5 + master clock input 12 v1Cv4, vsg1Cvsg4, subck to v-driver 3v driver supply vsub to ccd rg, h1Ch4 to ccd + + top view ad9995 pin 1 i dentifier 42 sdi 41 sl 40 refb 39 reft 38 avss 37 ccdin 36 avdd 35 cli 34 clo 33 tcvdd 32 tcvss 31 rgvdd 30 rg 29 rgvss d5 1 d6 2 d7 3 d8 4 d9 5 d10 6 d11 7 drvdd 8 drvss 9 vsub 10 subck 11 v1 12 v2 13 v3 14 56 d4 55 d3 54 d2 53 d1 52 d0 51 dclk 50 hd 49 dvdd 48 dvss 47 vd 46 sync 45 strobe 44 mshut 43 sck v4 15 v5 16 v6 17 vsg1 18 vsg2 19 vsg3 20 vsg4 21 vsg5 22 h1 23 h2 24 hvss 25 hvdd 26 h3 27 h4 28 + 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 4.7f 4.7f 4.7f 4.7f 1f 1f figure 38. typical circuit confguration rev. 0 rev. 0 obsolete
ad9995 C36C ad9995 C37C serial interface timing all of the internal registers of the ad9995 are accessed through a 3-wire serial interface. each register consists of an 8-bit address and a 24-bit data-word. both the 8-bit address and 24-bit data- word are written starting with the lsb. to write to each register, a 32-bit operation is required, as shown in figure 40a. although many registers are fewer than 24 bits wide, all 24 bits must be written for each register. for example, if the register is only 10 bits wide, the upper 14 bits are dont cares and may be flled with 0s during the serial write operation. if fewer than 24 bits are written, the register will not be updated with new data. sdata a0 a1 a2 a4 a5 a6 a7 d0 d1 d2 d3 d21 d22 d23 sck sl a3 notes 1. sdata bits are latched on sck rising edges. sck may idle high or low in between write operations. 2. all 32 bits must be written: 8 bits for address and 24 bits for d ata. 3. if the register length is <24 bits, dont care bits must be used to complete the 24-bit data length. 4. new data values are updated in the specified register location at different times, depending on the particular register written to. see the register updates sect ion for more information. t dh t ls t lh t ds ... ... ... 8-bit address 24-bit data 1 32 2 3 4 5 6 7 8 9 10 11 12 30 31 figure 40a. serial write operation sdata a0 a1 a2 a4 a5 a6 a7 d0 d1 d22 d23 sck sl a3 notes 1. multiple sequential registers may be loaded continuously. 2. the first (lowest address) register address is written, follow ed by multiple 24-bit data-words. 3. the address will automatically increment with each 24-bit data- word (all 24 bits must be written). 4. sl is held low until the last desired register has been loaded . d0 d1 d22 d23 d0 ... ... ... data for starting register address data for next register address d2d1 ... ... ... ... ... ... 1 32 2 3 4 5 6 7 8 9 10 31 3433 5655 58 57 59 figure 40b. continuous serial write operation figure 40b shows a more effcient way to write to the registers, using the ad9995s address auto-increment capability. using this method, the lowest desired address is written frst, followed by multiple 24-bit data-words. each new 24-bit data-word will automatically be written to the next highest register address. by eliminating the need to write each 8-bit address, faster register loading is achieved. continuous write operations may be used starting with any register location, and may be used to write to as few as two registers, or as many as the entire register space. rev. 0 rev. 0 obsolete
ad9995 C38 C register address banks 1 and 2 the ad9995 address space is divided into two different regis- ter banks, referred to as register bank 1 and register bank 2. figure 41 illustrates how the two banks are divided. register bank 1 contains the registers for the afe, miscellaneous func- tions, vd/hd parameters, timing core, clpob masking, vsg patterns, and shutter functions. register bank 2 contains all of the information for the v-pattern groups, v-sequences, and f eld information. afe registers switch to register bank 2 register bank 1 addr 0x00 addr 0x7f miscellaneous registers vd/hd registers timing core registers clpob mask registers vsg pattern registers shutter registers addr 0x10 addr 0x20 addr 0x30 addr 0x40 addr 0x50 addr 0x60 vpat0Cvpat9 registers switch to register bank 1 register bank 2 addr 0x00 vseq0Cvseq9 registers field 0Cfield 5 registers addr 0x7f addr 0x80 addr 0xd0 addr 0xff addr 0x7e addr 0xcf write to address 0x7f to switch register banks addr 0xff addr 0x8f invaliddo not access figure 41. layout of internal register banks 1 and 2 when writing to the ad9995, address 0x7f is used to specify which address bank is being written to. to write to bank 1, the lsb of address 0x7f should be set to 0; to write to bank 2, the lsb of address 0x7f should be set to 1. note that register bank 1 contains many unused addresses. any undef ned addresses between 0x00 and 0x7f are considered dont cares, and it is acceptable if these addresses are f lled in with all 0s during a continuous register write operation. however, the undef ned addresses above 0x7f must not be written to, or the ad9995 may not operate properly. rev. 0 obsolete
ad9995 C39 C updating new register values the ad9995s internal registers are updated at different times, depending on the particular register. table xv summarizes the four different types of register updates: 1. sck updated : some of the registers in bank 1 are updated immediately, as soon as the 24th data bit (d23) is written. these registers are used for functions that do not require gat- ing with the next vd boundary, such as power-up and reset functions. these registers are lightly shaded in gray in the bank 1 register list. the bank select register (addr. 0x7f in bank 1 and 2) is also sck updated. 2. vd updated : most of the registers in bank 1, as well as the field registers in bank 2, are updated at the next vd falling edge. by updating these values at the next vd edge, the cur- rent f eld will not be corrupted and the new register values will be applied to the next f eld. the bank 1 register updates may be further delayed past the vd falling edge by using the update register (addr. 0x19). this will delay the vd updated register updates to any hd line in the f eld. note that the bank 2 registers are not affected by the update register. 3. sg-line updated : a few of the registers in bank 1 are updated at the end of the sg active line, at the hd falling edge. these are the registers to control the subck signal so that the subck output will not be updated until after the sg line has been completed. these registers are darkly shaded in gray in the bank 1 register list. 4. scp updated : in bank 2, all of the v-pattern group and v-sequence registers (addr. 0x00 through 0xcf, exclud- ing 0x7f) are updated at the next scp, where they will be used. for example, in figure 42, this f eld has selected region 1 to use v-sequence 3 for the vertical outputs. this means that a write to any of the v-sequence 3 registers, or any of the v-pattern group registers that are referenced by v-sequence 3 will be updated at scp1. if multiple writes are done to the same register, the last one done before scp1 will be the one that is updated. likewise, register writes to any v-sequence 5 registers will be updated at scp2, and register writes to any v-sequence 8 registers will be updated at scp3. table xv. register update locations update type register bank description sck updated bank 1 only register is immediately updated when the 24th data bit (d23) is clocked in. vd updated bank 1 and bank 2 register is updated at the vd falling edge. vd updated registers in bank 1 may be delayed further by using the update register at address 0x19 in bank 1. bank 2 updates will not be affected by the update register. sg line updated bank 1 only register is updated at the hd falling edge at the end of the sg-active line. scp updated bank 2 only register is updated at the next scp when the register will be used. vd region 0 hd scp 1 scp 2 scp 3 region 1 region 2 region 3 vsg sgline sgline scp 0 serial writ e sc k updated scp 0 vd updated sg updated sc p updated v1Cv 6 use vseq 2 use vseq 3 use vseq 5 use vseq 8 figure 42. register update locations (see table xv for def nitions) rev. 0 obsolete
ad9995 C40 C complete listing for register bank 1 all registers are vd updated, except where noted: = sck updated = sg-line updated all address and default values are in hexadecimal. table xvi. afe register map data bit default address content value register name register description 00 [11:0] 7 oprmode afe operation modes (see table xxiv for detail). 01 [9:0] 0 vgagain vga gain. 02 [7:0] 80 clamplevel optical black clamp level. 03 [11:0] 4 ctlmode afe control modes (see table xxv for detail). table xvii. miscellaneous register map data bit default address content value register name register description 10 [0] 0 sw_rst software reset. 1 = reset all registers to default, then self-clear back to 0. 11 [0] 0 outcontrol output control. 0 = make all outputs dc inactive. 12 [0] 1 test use internal use only. must be set to 1. 13 [0] 0 syncpol sync active polarity (0 = active low). 14 [0] 0 syncsuspend suspend clocks during sync active (1 = suspend). 15 [0] 0 tgcore_rstb timing core reset bar. 0 = reset tg core, 1 = resume operation. 16 [0] 1 osc_pwrdown clo oscillator power-down (0 = oscillator is powered-down). 17 unused. 18 [0] 0 test use internal use only. must be set to 0. 19 [11:0] 0 update serial update. line (hd) in the f eld to update vd updated registers. 1a [0] 0 preventupdate prevents the update of the vd updated registers. 1 = prevent update. 1b [23:0] 0 mode mode register. 1c [1:0] 0 fieldval field value sync. 0 = next field 0, 1 = next field 1, 2/3 = next field 2. table xviii. vd/hd register map data bit default address content value register name register description 20 [0] 0 master vd/hd master or slave timing (0 = slave mode). 21 [0] 0 vdhdpol vd/hd active polarity. 0 = low, 1 = high. 22 [17:0] 0 vdhdrise rising edge location for vd [17:12] and hd [11:0]. rev. 0 obsolete
ad9995 C41 C table xix. timing core register map data bit default address content value register name register description 30 [0] 0 clidivide divide cli input clock by 2. 1 = divide by 2. 31 [12:0] 01001 h1control h1 signal control: polarity [0](0 = inversion, 1 = no inversion). h1 positive edge location [6:1]. h1 negative edge location [12:7]. 32 [12:0] 01001 h3control h3 signal control: polarity [0](0 = inversion, 1 = no inversion). h3 positive edge location [6:1]. h3 negative edge location [12:7]. 33 [12:0] 00801 rgcontrol rg signal control: polarity [0](0 = inversion, 1 = no inversion). rg positive edge location [6:1]. rg negative edge location [12:7]. 34 [1:0] 0 hblkretime retime hblk to internal h1/h3 clocks. h1 retime [0]. h3 retime [1]. preferred setting is 1 for each bit. setting each bit to 1 will add one cycle delay to hblk toggle positions. 35 [14:0] 1249 drvcontrol drive strength control for h1 [2:0], h2 [5:3], h3 [8:6], h4 [11:9], and rg [14:12]. drive current values: 0 = off, 1 = 4.3 ma, 2 = 8.6 ma, 3 = 12.9 ma, 4 = 17.2 ma, 5 = 21.5 ma, 6 = 25.8 ma, 7 = 30.1 ma. 36 [11:0] 00024 sampcontrol shp/shd sample control: shp sampling location [5:0]. shd sampling location [11:6]. 37 [8:0] 100 doutcontrol dout phase control [5:0]. dclk mode [6]. doutdelay [8:7]. table xx. clpob masking register map data bit default address content value register name register description 40 [23:0] ffffff clpmask01 clpob line masking. line #0 [11:0]. line #1 [23:0]. 41 [23:0] ffffff clpmask23 clpob line masking. line #2 [11:0]. line #3 [23:0]. 42 [11:0] ffffff clpmask4 clpob line masking. line #4 [11:0]. table xxi. sg pattern register map data bit default address content value register name register description 50 [3:0] f sgpol start polarity for sg patterns. pattern #0 [0]. pattern #1 [1]. pattern #2 [2]. pattern #3 [3]. 51 [23:0] ffffff sgtog12_0 pattern #0. toggle position 1 [11:0]. toggle position 2 [23:12]. 52 [23:0] ffffff sgtog12_1 pattern #1. toggle position 1 [11:0]. toggle position 2 [23:12]. 53 [23:0] ffffff sgtog12_2 pattern #2. toggle position 1 [11:0]. toggle position 2 [23:12]. 54 [23:0] ffffff sgtog12_3 pattern #3. toggle position 1 [11:0]. toggle position 2 [23:12]. table xxii. shutter control register map data bit default address content value register name register description 60 [4:0] 0 trigger trigger for vsub [0], mshut [1], strobe [2], exposure [3], and readout [4]. note that to trigger the readout to automatically occur after the exposure period, both exposure and readout should be triggered together. 61 [2:0] 2 readout number of fields to suppress the subck pulses after the vsg line. 62 [11:0] 0 exposure number of fields to suppress the subck and vsg pulses. [12] 0 vdhdoff set = 1 to disable the vd/hd outputs during exposure (when >1 f eld). 63 [11:0] 0 subcksuppress number of subck pulses to suppress after vsg line. [23:12] 0 subcknum number of subck pulses per field. 64 [0] 1 subckpol subck pulse start polarity. 65 [23:0] ffffff subck1tog first subck pulse. toggle position 1 [11:0]. toggle position 2 [23:0]. 66 [23:0] ffffff subck2tog second subck pulse. toggle position 1 [11:0]. toggle position 2 [23:0]. rev. 0 obsolete
ad9995 C42 C table xxii. shutter control register map (continued) data bit default address content value register name register description 67 [1:0] 0 vsubmode vsub readout mode [0]. vsub keep-on mode [1]. 68 [12:0] 1000 vsubon vsub on position [11:0]. vsub active polarity [12]. 69 [1:0] 1 mshutpol mshut active polarity [0]. mshut manual enable [1]. 6a [23:0] 0 mshuton mshut on position. line [11:0]. pixel [23:0]. 6b [11:0] 0 mshutoff_fd mshut off field position. 6c [23:0] 0 mshutoff_lnpx mshut off position. line [11:0]. pixel [23:12]. 6d [0] 1 strobpol strobe active polarity. 6e [11:0] 0 strobon_fd strobe on field position. 6f [23:0] 0 strobon_lnpx strobe on position. line [11:0]. pixel [23:12]. 70 [11:0] 0 stroboff_fd strobe off field position. 71 [23:0] 0 stroboff_lnpx strobe off position. line [11:0]. pixel [23:12]. table xxiii. register map selection data bit default address content value register name register description 7f [0] 0 bankselect1 register bank access from bank 1 to bank 2. 0 = bank 1, 1 = bank 2. table xxiv. afe operation register detail data bit default address content value register name register description 00 [1:0] 3 pwrdown 0 = normal operation, 1 = standby 1, 2 = standby 2, 3 = standby 3. [2] 1 clpenable 0 = disable ob clamp, 1 = enable ob clamp. [3] 0 clpspeed 0 = select normal ob clamp settling, 1 = select fast ob clamp settling. [4] 0 test test use only. set to 0. [5] 0 pblk_lvl dout value during pblk: 0 = blank to zero, 1 = blank to clamp level. [7:6] 0 test test use only. set to 0. [8] 0 dcbyp 0 = enable dc restore circuit, 1 = bypass dc restore circuit during pblk. [9] 0 test test use only. set to 0. table xxv. afe control register detail data bit default address content value register name register description 03 [1:0] 0 test test use only. set to 00. [2] 1 test test use only. set to 1. [3] 0 doutdisable 0 = data outputs are driven, 1 = data outputs are three-stated. [4] 0 doutlatch 0 = latch data outputs with dout phase, 1 = output latch transparent. [5] 0 grayencode 0 = binary encode data outputs, 1 = gray encode data outputs. rev. 0 obsolete
ad9995 C43 C complete listing for register bank 2 all v-pattern group and v-sequence registers are scp updated, and all field registers are vd updated. all address and default values are in hexadecimal. table xxvi. v-pattern group 0 (vpat0) register map data bit default address content value register name description 00 [5:0] 0 vpol_0 vpat0 start polarity. v1[0]. v2[1]. v3[2]. v4[3]. v5[4]. v6[5]. [11:6] 0 unused unused. [23:12] 0 v patlen _0 total length of vpat0. note: if using vpat0 as a second v-sequence in the vsg active line, this value is the start position for the second v-sequence. 01 [11:0] 0 v1tog1 _0 v1 toggle position 1 [23:12] 0 v1tog2 _0 v1 toggle position 2 02 [11:0] 0 v1tog3 _0 v1 toggle position 3 [23:12] 0 v2tog1 _0 v2 toggle position 1 03 [11:0] 0 v2tog2 _0 v2 toggle position 2 [23:12] 0 v2tog3 _0 v2 toggle position 3 04 [11:0] 0 v3tog1 _0 v3 toggle position 1 [23:12] 0 v3tog2 _0 v3 toggle position 2 05 [11:0] 0 v3tog3 _0 v3 toggle position 3 [23:12] 0 v4tog1 _0 v4 toggle position 1 06 [11:0] 0 v4tog2 _0 v4 toggle position 2 [23:12] 0 v4tog3 _0 v4 toggle position 3 07 [11:0] 0 v5tog1 _0 v5 toggle position 1 [23:12] 0 v5tog2 _0 v5 toggle position 2 08 [11:0] 0 v5tog3 _0 v5 toggle position 3 [23:12] 0 v6tog1 _0 v6 toggle position 1 09 [11:0] 0 v6tog2 _0 v6 toggle position 2 [23:12] 0 v6tog3 _0 v6 toggle position 3 0a [11:0] 0 freeze1 _0 v1Cv6 freeze position 1 [23:12] 0 resume1 _0 v1Cv6 resume position 1 0b [11:0] 0 freeze2 _0 v1Cv6 freeze position 2 [23:12] 0 resume2 _0 v1Cv6 resume position 2 table xxvii. v-pattern group 1 (vpat1) register map data bit default address content value register name description 0c [5:0] 0 vpol_1 vpat1 start polarity. v1[0]. v2[1]. v3[2]. v4[3]. v5[4]. v6[5]. [11:6] 0 unused unused. [23:12] 0 v patlen _1 total length of vpat1. note: if using vpat1 as a second v-sequence in the vsg active line, this value is the start position for the second v-sequence. 0d [11:0] 0 v1tog1 _1 v1 toggle position 1 [23:12] 0 v1tog2 _1 v1 toggle position 2 0e [11:0] 0 v1tog3 _1 v1 toggle position 3 [23:12] 0 v2tog1 _1 v2 toggle position 1 0f [11:0] 0 v2tog2 _1 v2 toggle position 2 [23:12] 0 v2tog3 _1 v2 toggle position 3 10 [11:0] 0 v3tog1 _1 v3 toggle position 1 [23:12] 0 v3tog2 _1 v3 toggle position 2 11 [11:0] 0 v3tog3 _1 v3 toggle position 3 [23:12] 0 v4tog1 _1 v4 toggle position 1 12 [11:0] 0 v4tog2 _1 v4 toggle position 2 [23:12] 0 v4tog3 _1 v4 toggle position 3 rev. 0 obsolete
ad9995 C44 C table xxvii. v-pattern group 1 (vpat1) register map (continued) data bit default address content value register name description 13 [11:0] 0 v5tog1 _1 v5 toggle position 1 [23:12] 0 v5tog2 _1 v5 toggle position 2 14 [11:0] 0 v5tog3 _1 v5 toggle position 3 [23:12] 0 v6tog1 _1 v6 toggle position 1 15 [11:0] 0 v6tog2 _1 v6 toggle position 2 [23:12] 0 v6tog3 _1 v6 toggle position 3 16 [11:0] 0 freeze1 _1 v1Cv6 freeze position 1 [23:12] 0 resume1 _1 v1Cv6 resume position 1 17 [11:0] 0 freeze2 _1 v1Cv6 freeze position 2 [23:12] 0 resume2 _1 v1Cv6 resume position 2 table xxviii. v-pattern group 2 (vpat2) register map data bit default address content value register name description 18 [5:0] 0 vpol_2 vpat2 start polarity. v1[0]. v2[1]. v3[2]. v4[3]. v5[4]. v6[5]. [11:6] 0 unused unused. [23:12] 0 v patlen _2 total length of vpat2. note: if using vpat2 as a second v-sequence in the vsg active line, this value is the start position for the second v-sequence. 19 [11:0] 0 v1tog1 _2 v1 toggle position 1 [23:12] 0 v1tog2 _2 v1 toggle position 2 1a [11:0] 0 v1tog3 _2 v1 toggle position 3 [23:12] 0 v2tog1 _2 v2 toggle position 1 1b [11:0] 0 v2tog2 _2 v2 toggle position 2 [23:12] 0 v2tog3 _2 v2 toggle position 3 1c [11:0] 0 v3tog1 _2 v3 toggle position 1 [23:12] 0 v3tog2 _2 v3 toggle position 2 1d [11:0] 0 v3tog3 _2 v3 toggle position 3 [23:12] 0 v4tog1 _2 v4 toggle position 1 1e [11:0] 0 v4tog2 _2 v4 toggle position 2 [23:12] 0 v4tog3 _2 v4 toggle position 3 1f [11:0] 0 v5tog1 _2 v5 toggle position 1 [23:12] 0 v5tog2 _2 v5 toggle position 2 20 [11:0] 0 v5tog3 _2 v5 toggle position 3 [23:12] 0 v6tog1 _2 v6 toggle position 1 21 [11:0] 0 v6tog2 _2 v6 toggle position 2 [23:12] 0 v6tog3 _2 v6 toggle position 3 22 [11:0] 0 freeze1 _2 v1Cv6 freeze position 1 [23:12] 0 resume1 _2 v1Cv6 resume position 1 23 [11:0] 0 freeze2 _2 v1Cv6 freeze position 2 [23:12] 0 resume2 _2 v1Cv6 resume position 2 table xxix. v-pattern group 3 (vpat3) register map data bit default address content value register name description 24 [5:0] 0 vpol_3 vpat3 start polarity. v1[0]. v2[1]. v3[2]. v4[3]. v5[4]. v6[5]. [11:6] 0 unused unused. [23:12] 0 v patlen _3 total length of vpat3. note: if using vpat3 as a second v-sequence in the vsg active line, this value is the start position for the second v-sequence. 25 [11:0] 0 v1tog1 _3 v1 toggle position 1 [23:12] 0 v1tog2 _3 v1 toggle position 2 rev. 0 obsolete
ad9995 C45 C table xxix. v-pattern group 3 (vpat3) register map (continued) data bit default address content value register name description 26 [11:0] 0 v1tog3 _3 v1 toggle position 3 [23:12] 0 v2tog1 _3 v2 toggle position 1 27 [11:0] 0 v2tog2 _3 v2 toggle position 2 [23:12] 0 v2tog3 _3 v2 toggle position 3 28 [11:0] 0 v3tog1 _3 v3 toggle position 1 [23:12] 0 v3tog2 _3 v3 toggle position 2 29 [11:0] 0 v3tog3 _3 v3toggle position 3 [23:12] 0 v4tog1 _3 v4 toggle position 1 2a [11:0] 0 v4tog2 _3 v4 toggle position 2 [23:12] 0 v4tog3 _3 v4 toggle position 3 2b [11:0] 0 v5tog1 _3 v5 toggle position 1 [23:12] 0 v5tog2 _3 v5 toggle position 2 2c [11:0] 0 v5tog3 _3 v5 toggle position 3 [23:12] 0 v6tog1 _3 v6 toggle position 1 2d [11:0] 0 v6tog2 _3 v6 toggle position 2 [23:12] 0 v6tog3 _3 v6 toggle position 3 2e [11:0] 0 freeze1 _3 v1Cv6 freeze position 1 [23:12] 0 resume1 _3 v1Cv6 resume position 1 2f [11:0] 0 freeze2 _3 v1Cv6 freeze position 2 [23:12] 0 resume2 _3 v1Cv6 resume position 2 table xxx. v-pattern group 4 (vpat4) register map data bit default address content value register name description 30 [5:0] 0 vpol_4 vpat4 start polarity. v1[0]. v2[1]. v3[2]. v4[3]. v5[4]. v6[5]. [11:6] 0 unused unused. [23:12] 0 v patlen _4 total length of vpat4. note: if using vpat4 as a second v-sequence in the vsg active line, this value is the start position for the second v-sequence. 31 [11:0] 0 v1tog1 _4 v1 toggle position 1 [23:12] 0 v1tog2 _4 v1 toggle position 2 32 [11:0] 0 v1tog3 _4 v1 toggle position 3 [23:12] 0 v2tog1 _4 v2 toggle position 1 33 [11:0] 0 v2tog2 _4 v2 toggle position 2 [23:12] 0 v2tog3 _4 v2 toggle position 3 34 [11:0] 0 v3tog1 _4 v3 toggle position 1 [23:12] 0 v3tog2 _4 v3 toggle position 2 35 [11:0] 0 v3tog3 _4 v3toggle position 3 [23:12] 0 v4tog1 _4 v4 toggle position 1 36 [11:0] 0 v4tog2 _4 v4 toggle position 2 [23:12] 0 v4tog3 _4 v4 toggle position 3 37 [11:0] 0 v5tog1 _4 v5 toggle position 1 [23:12] 0 v5tog2 _4 v5 toggle position 2 38 [11:0] 0 v5tog3 _4 v5 toggle position 3 [23:12] 0 v6tog1 _4 v6 toggle position 1 39 [11:0] 0 v6tog2 _4 v6 toggle position 2 [23:12] 0 v6tog3 _4 v6 toggle position 3 3a [11:0] 0 freeze1 _4 v1Cv6 freeze position 1 [23:12] 0 resume1 _4 v1Cv6 resume position 1 3b [11:0] 0 freeze2 _4 v1Cv6 freeze position 2 [23:12] 0 resume2 _4 v1Cv6 resume position 2 rev. 0 obsolete
ad9995 C46 C table xxxi. v-pattern group 5 (vpat5) register map data bit default address content value register name description 3c [5:0] 0 vpol_5 vpat5 start polarity. v1[0]. v2[1]. v3[2]. v4[3]. v5[4]. v6[5]. [11:6] 0 unused unused. [23:12] 0 v patlen _5 total length of vpat5. note: if using vpat5 as a second v-sequence in the vsg active line, this value is the start position for the second v-sequence. 3d [11:0] 0 v1tog1 _5 v1 toggle position 1 [23:12] 0 v1tog2 _5 v1 toggle position 2 3e [11:0] 0 v1tog3 _5 v1 toggle position 3 [23:12] 0 v2tog1 _5 v2 toggle position 1 3f [11:0] 0 v2tog2 _5 v2 toggle position 2 [23:12] 0 v2tog3 _5 v2 toggle position 3 40 [11:0] 0 v3tog1 _5 v3 toggle position 1 [23:12] 0 v3tog2 _5 v3 toggle position 2 41 [11:0] 0 v3tog3 _5 v3 toggle position 3 [23:12] 0 v4tog1 _5 v4 toggle position 1 42 [11:0] 0 v4tog2 _5 v4 toggle position 2 [23:12] 0 v4tog3 _5 v4 toggle position 3 43 [11:0] 0 v5tog1 _5 v5 toggle position 1 [23:12] 0 v5tog2 _5 v5 toggle position 2 44 [11:0] 0 v5tog3 _5 v5 toggle position 3 [23:12] 0 v6tog1 _5 v6 toggle position 1 45 [11:0] 0 v6tog2 _5 v6 toggle position 2 [23:12] 0 v6tog3 _5 v6 toggle position 3 46 [11:0] 0 freeze1 _5 v1Cv6 freeze position 1 [23:12] 0 resume1 _5 v1Cv6 resume position 1 47 [11:0] 0 freeze2 _5 v1Cv6 freeze position 2 [23:12] 0 resume2 _5 v1Cv6 resume position 2 table xxxii. v-pattern group 6 (vpat6) register map data bit default address content value register name description 48 [5:0] 0 vpol_6 vpat6 start polarity. v1[0]. v2[1]. v3[2]. v4[3]. v5[4]. v6[5]. [11:6] 0 unused unused. [23:12] 0 v patlen _6 total length of vpat6. note: if using vpat6 as a second v-sequence in the vsg active line, this value is the start position for the second v-sequence. 49 [11:0] 0 v1tog1 _6 v1 toggle position 1 [23:12] 0 v1tog2 _6 v1 toggle position 2 4a [11:0] 0 v1tog3 _6 v1 toggle position 3 [23:12] 0 v2tog1 _6 v2 toggle position 1 4b [11:0] 0 v2tog2 _6 v2 toggle position 2 [23:12] 0 v2tog3 _6 v2 toggle position 3 4c [11:0] 0 v3tog1 _6 v3 toggle position 1 [23:12] 0 v3tog2 _6 v3 toggle position 2 4d [11:0] 0 v3tog3 _6 v3 toggle position 3 [23:12] 0 v4tog1 _6 v4 toggle position 1 4e [11:0] 0 v4tog2 _6 v4 toggle position 2 [23:12] 0 v4tog3 _6 v4 toggle position 3 4f [11:0] 0 v5tog1 _6 v5 toggle position 1 [23:12] 0 v5tog2 _6 v5 toggle position 2 rev. 0 obsolete
ad9995 C47 C table xxxii. v-pattern group 6 (vpat6) register map (continued) data bit default address content value register name description 50 [11:0] 0 v5tog3 _6 v5 toggle position 3 [23:12] 0 v6tog1 _6 v6 toggle position 1 51 [11:0] 0 v6tog2 _6 v6 toggle position 2 [23:12] 0 v6tog3 _6 v6 toggle position 3 52 [11:0] 0 freeze1 _6 v1Cv6 freeze position 1 [23:12] 0 resume1 _6 v1Cv6 resume position 1 53 [11:0] 0 freeze2 _6 v1Cv6 freeze position 2 [23:12] 0 resume2 _6 v1Cv6 resume position 2 table xxxiii. v-pattern group 7 (vpat7) register map data bit default address content value register name description 54 [5:0] 0 vpol_7 vpat7 start polarity. v1[0]. v2[1]. v3[2]. v4[3]. v5[4]. v6[5]. [11:6] 0 unused unused. [23:12] 0 v patlen _7 total length of vpat7. note: if using vpat7 as a second v-sequence in the vsg active line, this value is the start position for the second v-sequence. 55 [11:0] 0 v1tog1 _7 v1 toggle position 1 [23:12] 0 v1tog2 _7 v1 toggle position 2 56 [11:0] 0 v1tog3 _7 v1 toggle position 3 [23:12] 0 v2tog1 _7 v2 toggle position 1 57 [11:0] 0 v2tog2 _7 v2 toggle position 2 [23:12] 0 v2tog3 _7 v2 toggle position 3 58 [11:0] 0 v3tog1 _7 v3 toggle position 1 [23:12] 0 v3tog2 _7 v3 toggle position 2 59 [11:0] 0 v3tog3 _7 v3 toggle position 3 [23:12] 0 v4tog1 _7 v4 toggle position 1 5a [11:0] 0 v4tog2 _7 v4 toggle position 2 [23:12] 0 v4tog3 _7 v4 toggle position 3 5b [11:0] 0 v5tog1 _7 v5 toggle position 1 [23:12] 0 v5tog2 _7 v5 toggle position 2 5c [11:0] 0 v5tog3 _7 v5 toggle position 3 [23:12] 0 v6tog1 _7 v6 toggle position 1 5d [11:0] 0 v6tog2 _7 v6 toggle position 2 [23:12] 0 v6tog3 _7 v6 toggle position 3 5e [11:0] 0 freeze1 _7 v1Cv6 freeze position 1 [23:12] 0 resume1 _7 v1Cv6 resume position 1 5f [11:0] 0 freeze2 _7 v1Cv6 freeze position 2 [23:12] 0 resume2 _7 v1Cv6 resume position 2 table xxxiv. v-pattern group 8 (vpat8) register map data bit default address content value register name description 60 [5:0] 0 vpol_8 vpat8 start polarity. v1[0]. v2[1]. v3[2]. v4[3]. v5[4]. v6[5]. [11:6] 0 unused unused. [23:12] 0 v patlen _8 total length of vpat8. note: if using vpat8 as a second v-sequence in the vsg active line, this value is the start position for the second v-sequence. 61 [11:0] 0 v1tog1 _8 v1 toggle position 1 [23:12] 0 v1tog2 _8 v1 toggle position 2 62 [11:0] 0 v1tog3 _8 v1 toggle position 3 [23:12] 0 v1tog4 _8 v1 toggle position 4 rev. 0 obsolete
ad9995 C48 C table xxxiv. v-pattern group 8 (vpat8) register map (continued) data bit default address content value register name description 63 [11:0] 0 v2tog1 _8 v2 toggle position 1 [23:12] 0 v2tog2 _8 v2 toggle position 2 64 [11:0] 0 v3tog3 _8 v2 toggle position 3 [23:12] 0 v3tog4 _8 v2 toggle position 4 65 [11:0] 0 v3tog1 _8 v3 toggle position 1 [23:12] 0 v4tog2 _8 v3 toggle position 2 66 [11:0] 0 v4tog3 _8 v3 toggle position 3 [23:12] 0 v4tog4 _8 v3 toggle position 4 67 [11:0] 0 v5tog1 _8 v4 toggle position 1 [23:12] 0 v5tog2 _8 v4 toggle position 2 68 [11:0] 0 v5tog3 _8 v4 toggle position 3 [23:12] 0 v6tog4 _8 v4 toggle position 4 69 [11:0] 0 v6tog1 _8 v5 toggle position 1 [23:12] 0 v6tog2 _8 v5 toggle position 2 6a [11:0] 0 v6tog3 _8 v5 toggle position 3 [23:12] 0 v6tog4 _8 v5 toggle position 4 6b [11:0] 0 v6tog1 _8 v6 toggle position 1 [23:12] 0 v6tog2 _8 v6 toggle position 2 6c [11:0] 0 v6tog3 _8 v6 toggle position 3 [23:12] 0 v6tog4 _8 v6 toggle position 4 6d [11:0] 0 freeze1 _8 v1Cv6 freeze position 1 [23:12] 0 resume1 _8 v1Cv6 resume position 1 6e [11:0] 0 freeze2 _8 v1Cv6 freeze position 2 [23:12] 0 resume2 _8 v1Cv6 resume position 2 6f unused unused table xxxv. v-pattern group 9 (vpat9) register map data bit default address content value register name description 70 [5:0] 0 vpol_9 vpat9 start polarity. v1[0]. v2[1]. v3[2]. v4[3]. v5[4]. v6[5]. [11:6] 0 unused unused. [23:12] 0 v patlen _9 total length of vpat9. note: if using vpat9 as a second v-sequence in the vsg active line, this value is the start position for the second v-sequence. 71 [11:0] 0 v1tog1 _9 v1 toggle position 1 [23:12] 0 v1tog2 _9 v1 toggle position 2 72 [11:0] 0 v1tog3 _9 v1 toggle position 3 [23:12] 0 v1tog4 _9 v1 toggle position 4 73 [11:0] 0 v2tog1 _9 v2 toggle position 1 [23:12] 0 v2tog2 _9 v2 toggle position 2 74 [11:0] 0 v3tog3 _9 v2 toggle position 3 [23:12] 0 v3tog4 _9 v2 toggle position 4 75 [11:0] 0 v3tog1 _9 v3 toggle position 1 [23:12] 0 v4tog2 _9 v3 toggle position 2 76 [11:0] 0 v4tog3 _9 v3 toggle position 3 [23:12] 0 v4tog4 _9 v3 toggle position 4 77 [11:0] 0 v5tog1 _9 v4 toggle position 1 [23:12] 0 v5tog2 _9 v4 toggle position 2 78 [11:0] 0 v5tog3 _9 v4 toggle position 3 [23:12] 0 v6tog4 _9 v4 toggle position 4 rev. 0 obsolete
ad9995 C49 C table xxxv. v-pattern group 9 (vpat9) register map (continued) data bit default address content value register name description 79 [11:0] 0 v6tog1 _9 v5 toggle position 1 [23:12] 0 v6tog2 _9 v5 toggle position 2 7a [11:0] 0 v6tog3 _9 v5 toggle position 3 [23:12] 0 v6tog4 _9 v5 toggle position 4 7b [11:0] 0 v6tog1 _9 v6 toggle position 1 [23:12] 0 v6tog2 _9 v6 toggle position 2 7c [11:0] 0 v6tog3 _9 v6 toggle position 3 [23:12] 0 v6tog4 _9 v6 toggle position 4 7d [11:0] 0 freeze1 _9 v1Cv6 freeze position 1 [23:12] 0 resume1 _9 v1Cv6 resume position 1 7e [11:0] 0 freeze2 _9 v1Cv6 freeze position 2 [23:12] 0 resume2 _9 v1Cv6 resume position 2 table xxxvi. register map selection (sck updated register) data bit default address content value register name register description 7f [0] 0 bankselect2 register bank access from bank 2 to bank 1. 0 = bank 1, 1 = bank 2. table xxxvii. v-sequence 0 (vseq0) register map data bit default address content value register name description 80 [1:0] 0 hblkmask_0 masking polarity during hblk. h1 [0]. h3 [1]. [2] 0 clpobpol _0 clpobpol _0 clpobpol clpob start polarity [3] 0 pblkpol _0 pblkpol _0 pblkpol pblk start polarity [7:4] 0 vpatsel _0 vpatsel _0 vpatsel selected v-pattern group for v-sequence 0 [9:8] 0 vmask _0 vmask _0 vmask enable masking of v-outputs (specif ed by freeze/resume registers) [11:10] 0 hblkalt_0 enable hblk alternation [23:12] 0 unused unused 81 [11:0] 0 vpatrepo _0 number of selected v-pattern group repetitions for odd lines [23:12] 0 vpatrepe _0 number of selected v-pattern group repetitions for even lines 82 [11:0] 0 vpatstart _0 start position in the line for the selected v-pattern group [23:12] 0 hdlen _0 hd line length (number of pixels) for v-sequence 0 83 [11:0] 0 pblktog1 _0 pblk toggle position 1 for v-sequence 0 [23:12] 0 pblktog2 _0 pblk toggle position 2 for v-sequence 0 84 [11:0] 0 hblktog1 _0 hblk toggle position 1 for v-sequence 0 [23:12] 0 hblktog2 _0 hblk toggle position 2 for v-sequence 0 85 [11:0] 0 hblktog3 _0 hblk toggle position 3 for v-sequence 0 [23:12] 0 hblktog4 _0 hblk toggle position 4 for v-sequence 0 86 [11:0] 0 hblktog5 _0 hblk toggle position 5 for v-sequence 0 [23:12] 0 hblktog6 _0 hblk toggle position 6 for v-sequence 0 87 [11:0] 0 clpobtog1 _0 clpob toggle position 1 for v-sequence 0 [23:12] 0 clpobtog2 _0 clpob toggle position 2 for v-sequence 0 rev. 0 obsolete
ad9995 C50 C table xxxviii. v-sequence 1 (vseq1) register map data bit default address content value register name description 88 [1:0] 0 hblkmask_1 masking polarity during hblk. h1 [0]. h3 [1]. [2] 0 clpobpol _1 clpobpol _1 clpobpol clpob start polarity [3] 0 pblkpol _1 pblkpol _1 pblkpol pblk start polarity [7:4] 0 vpatsel _1 vpatsel _1 vpatsel selected v-pattern group for v-sequence 1 [9:8] 0 vmask _1 vmask _1 vmask enable masking of v-outputs (specif ed by freeze/resume registers) [11:10] 0 hblkalt_1 enable hblk alternation [23:12] 0 unused unused 89 [11:0] 0 vpatrepo _1 number of selected v-pattern group repetitions for odd lines [23:12] 0 vpatrepe _1 number of selected v-pattern group repetitions for even lines 8a [11:0] 0 vpatstart _1 start position in the line for the selected v-pattern group [23:12] 0 hdlen _1 hd line length (number of pixels) for v-sequence 1 8b [11:0] 0 pblktog1 _1 pblk toggle position 1 for v-sequence 1 [23:12] 0 pblktog2 _1 pblk toggle position 2 for v-sequence 1 8c [11:0] 0 hblktog1 _1 hblk toggle position 1 for v-sequence 1 [23:12] 0 hblktog2 _1 hblk toggle position 2 for v-sequence 1 8d [11:0] 0 hblktog3 _1 hblk toggle position 3 for v-sequence 1 [23:12] 0 hblktog4 _1 hblk toggle position 4 for v-sequence 1 8e [11:0] 0 hblktog5 _1 hblk toggle position 5 for v-sequence 1 [23:12] 0 hblktog6 _1 hblk toggle position 6 for v-sequence 1 8f [11:0] 0 clpobtog1 _1 clpob toggle position 1 for v-sequence 1 [23:12] 0 clpobtog2 _1 clpob toggle position 2 for v-sequence 1 table xxxix. v-sequence 2 (vseq2) register map data bit default address content value register name description 90 [1:0] 0 hblkmask_2 masking polarity during hblk. h1 [0]. h3 [1]. [2] 0 clpobpol _2 clpobpol _2 clpobpol clpob start polarity [3] 0 pblkpol _2 pblkpol _2 pblkpol pblk start polarity [7:4] 0 vpatsel _2 vpatsel _2 vpatsel selected v-pattern group for v-sequence 2 [9:8] 0 vmask _2 vmask _2 vmask enable masking of v-outputs (specif ed by freeze/resume registers) [11:10] 0 hblkalt_2 enable hblk alternation [23:12] 0 unused unused 91 [11:0] 0 vpatrepo _2 number of selected v-pattern group repetitions for odd lines [23:12] 0 vpatrepe _2 number of selected v-pattern group repetitions for even lines 92 [11:0] 0 vpatstart _2 start position in the line for the selected v-pattern group [23:12] 0 hdlen _2 hd line length (number of pixels) for v-sequence 2 93 [11:0] 0 pblktog1 _2 pblk toggle position 1 for v-sequence 2 [23:12] 0 pblktog2 _2 pblk toggle position 2 for v-sequence 2 94 [11:0] 0 hblktog1 _2 hblk toggle position 1 for v-sequence 2 [23:12] 0 hblktog2 _2 hblk toggle position 2 for v-sequence 2 95 [11:0] 0 hblktog3 _2 hblk toggle position 3 for v-sequence 2 [23:12] 0 hblktog4 _2 hblk toggle position 4 for v-sequence 2 96 [11:0] 0 hblktog5 _2 hblk toggle position 5 for v-sequence 2 [23:12] 0 hblktog6 _2 hblk toggle position 6 for v-sequence 2 97 [11:0] 0 clpobtog1 _2 clpob toggle position 1 for v-sequence 2 [23:12] 0 clpobtog2 _2 clpob toggle position 2 for v-sequence 2 rev. 0 obsolete
ad9995 C51 C table xl. v-sequence 3 (vseq3) register map data bit default address content value register name description 98 [1:0] 0 hblkmask_3 masking polarity during hblk. h1 [0]. h3 [1]. [2] 0 clpobpol _3 clpobpol _3 clpobpol clpob start polarity [3] 0 pblkpol _3 pblkpol _3 pblkpol pblk start polarity [7:4] 0 vpatsel _3 vpatsel _3 vpatsel selected v-pattern group for v-sequence 3 [9:8] 0 vmask _3 vmask _3 vmask enable masking of v-outputs (specif ed by freeze/resume registers) [11:10] 0 hblkalt_3 enable hblk alternation [23:12] 0 unused unused 99 [11:0] 0 vpatrepo _3 number of selected v-pattern group repetitions for odd lines [23:12] 0 vpatrepe _3 number of selected v-pattern group repetitions for even lines 9a [11:0] 0 vpatstart _3 start position in the line for the selected v-pattern group [23:12] 0 hdlen _3 hd line length (number of pixels) for v-sequence 3 9b [11:0] 0 pblktog1 _3 pblk toggle position 1 for v-sequence 3 [23:12] 0 pblktog2 _3 pblk toggle position 2 for v-sequence 3 9c [11:0] 0 hblktog1 _3 hblk toggle position 1 for v-sequence 3 [23:12] 0 hblktog2 _3 hblk toggle position 2 for v-sequence 3 9d [11:0] 0 hblktog3 _3 hblk toggle position 3 for v-sequence 3 [23:12] 0 hblktog4 _3 hblk toggle position 4 for v-sequence 3 9e [11:0] 0 hblktog5 _3 hblk toggle position 5 for v-sequence 3 [23:12] 0 hblktog6 _3 hblk toggle position 6 for v-sequence 3 9f [11:0] 0 clpobtog1 _3 clpob toggle position 1 for v-sequence 3 [23:12] 0 clpobtog2 _3 clpob toggle position 2 for v-sequence 3 table xli. v-sequence 4 (vseq4) register map data bit default address content value register name description a0 [1:0] 0 hblkmask_4 masking polarity during hblk. h1 [0]. h3 [1]. [2] 0 clpobpol _4 clpobpol _4 clpobpol clpob start polarity [3] 0 pblkpol _4 pblkpol _4 pblkpol pblk start polarity [7:4] 0 vpatsel _4 vpatsel _4 vpatsel selected v-pattern group for v-sequence 4 [9:8] 0 vmask _4 vmask _4 vmask enable masking of v-outputs (specif ed by freeze/resume registers) [11:10] 0 hblkalt_4 enable hblk alternation [23:12] 0 unused unused a1 [11:0] 0 vpatrepo _4 number of selected v-pattern group repetitions for odd lines [23:12] 0 vpatrepe _4 number of selected v-pattern group repetitions for even lines a2 [11:0] 0 vpatstart _4 start position in the line for the selected v-pattern group [23:12] 0 hdlen _4 hd line length (number of pixels) for v-sequence 4 a3 [11:0] 0 pblktog1 _4 pblk toggle position 1 for v-sequence 4 [23:12] 0 pblktog2 _4 pblk toggle position 2 for v-sequence 4 a4 [11:0] 0 hblktog1 _4 hblk toggle position 1 for v-sequence 4 [23:12] 0 hblktog2 _4 hblk toggle position 2 for v-sequence 4 a5 [11:0] 0 hblktog3 _4 hblk toggle position 3 for v-sequence 4 [23:12] 0 hblktog4 _4 hblk toggle position 4 for v-sequence 4 a6 [11:0] 0 hblktog5 _4 hblk toggle position 5 for v-sequence 4 [23:12] 0 hblktog6 _4 hblk toggle position 6 for v-sequence 4 a7 [11:0] 0 clpobtog1 _4 clpob toggle position 1 for v-sequence 4 [23:12] 0 clpobtog2 _4 clpob toggle position 2 for v-sequence 4 rev. 0 obsolete
ad9995 C52 C table xlii. v-sequence 5 (vseq5) register map data bit default address content value register name description a8 [1:0] 0 hblkmask_5 masking polarity during hblk. h1 [0]. h3 [1]. [2] 0 clpobpol _5 clpobpol _5 clpobpol clpob start polarity [3] 0 pblkpol _5 pblkpol _5 pblkpol pblk start polarity [7:4] 0 vpatsel _5 vpatsel _5 vpatsel selected v-pattern group for v-sequence 5 [9:8] 0 vmask _5 vmask _5 vmask enable masking of v-outputs (specif ed by freeze/resume registers) [11:10] 0 hblkalt_5 enable hblk alternation [23:12] 0 unused unused a9 [11:0] 0 vpatrepo _5 number of selected v-pattern group repetitions for odd lines [23:12] 0 vpatrepe _5 number of selected v-pattern group repetitions for even lines aa [11:0] 0 vpatstart _5 start position in the line for the selected v-pattern group [23:12] 0 hdlen _5 hd line length (number of pixels) for v-sequence 5 ab [11:0] 0 pblktog1 _5 pblk toggle position 1 for v-sequence 5 [23:12] 0 pblktog2 _5 pblk toggle position 2 for v-sequence 5 ac [11:0] 0 hblktog1 _5 hblk toggle position 1 for v-sequence 5 [23:12] 0 hblktog2 _5 hblk toggle position 2 for v-sequence 5 ad [11:0] 0 hblktog3 _5 hblk toggle position 3 for v-sequence 5 [23:12] 0 hblktog4 _5 hblk toggle position 4 for v-sequence 5 ae [11:0] 0 hblktog5 _5 hblk toggle position 5 for v-sequence 5 [23:12] 0 hblktog6 _5 hblk toggle position 6 for v-sequence 5 af [11:0] 0 clpobtog1 _5 clpob toggle position 1 for v-sequence 5 [23:12] 0 clpobtog2 _5 clpob toggle position 2 for v-sequence 5 table xliii. v-sequence 6 (vseq6) register map data bit default address content value register name description b0 [1:0] 0 hblkmask_6 masking polarity during hblk. h1 [0]. h3 [1]. [2] 0 clpobpol _6 clpobpol _6 clpobpol clpob startpolarity [3] 0 pblkpol _6 pblkpol _6 pblkpol pblk start polarity [7:4] 0 vpatsel _6 vpatsel _6 vpatsel selected v-pattern group for v-sequence 6 [9:8] 0 vmask _6 vmask _6 vmask enable masking of v-outputs (specif ed by freeze/resume registers) [11:10] 0 hblkalt_6 enable hblk alternation [23:12] 0 unused unused b1 [11:0] 0 vpatrepo _6 number of selected v-pattern group repetitions for odd lines [23:12] 0 vpatrepe _6 number of selected v-pattern group repetitions for even lines b2 [11:0] 0 vpatstart _6 start position in the line for the selected v-pattern group [23:12] 0 hdlen _6 hd line length (number of pixels) for v-sequence 6 b3 [11:0] 0 pblktog1 _6 pblk toggle position 1 for v-sequence 6 [23:12] 0 pblktog2 _6 pblk toggle position 2 for v-sequence 6 b4 [11:0] 0 hblktog1 _6 hblk toggle position 1 for v-sequence 6 [23:12] 0 hblktog2 _6 hblk toggle position 2 for v-sequence 6 b5 [11:0] 0 hblktog3 _6 hblk toggle position 3 for v-sequence 6 [23:12] 0 hblktog4 _6 hblk toggle position 4 for v-sequence 6 b6 [11:0] 0 hblktog5 _6 hblk toggle position 5 for v-sequence 6 [23:12] 0 hblktog6 _6 hblk toggle position 6 for v-sequence 6 b7 [11:0] 0 clpobtog1 _6 clpob toggle position 1 for v-sequence 6 [23:12] 0 clpobtog2 _6 clpob toggle position 2 for v-sequence 6 rev. 0 obsolete
ad9995 C53 C table xliv. v-sequence 7 (vseq7) register map data bit default address content value register name description b8 [1:0] 0 hblkmask_7 masking polarity during hblk. h1 [0]. h3 [1]. [2] 0 clpobpol _7 clpobpol _7 clpobpol clpob start polarity [3] 0 pblkpol _7 pblkpol _7 pblkpol pblk start polarity [7:4] 0 vpatsel _7 vpatsel _7 vpatsel selected v-pattern group for v-sequence 7 [9:8] 0 vmask _7 vmask _7 vmask enable masking of v-outputs (specif ed by freeze/resume registers) [11:10] 0 hblkalt_7 enable hblk alternation [23:12] 0 unused unused b9 [11:0] 0 vpatrepo _7 number of selected v-pattern group repetitions for odd lines [23:12] 0 vpatrepe _7 number of selected v-pattern group repetitions for even lines ba [11:0] 0 vpatstart _7 start position in the line for the selected v-pattern group [23:12] 0 hdlen _7 hd line length (number of pixels) for v-sequence 7 bb [11:0] 0 pblktog1 _7 pblk toggle position 1 for v-sequence 7 [23:12] 0 pblktog2 _7 pblk toggle position 2 for v-sequence 7 bc [11:0] 0 hblktog1 _7 hblk toggle position 1 for v-sequence 7 [23:12] 0 hblktog2 _7 hblk toggle position 2 for v-sequence 7 bd [11:0] 0 hblktog3 _7 hblk toggle position 3 for v-sequence 7 [23:12] 0 hblktog4 _7 hblk toggle position 4 for v-sequence 7 be [11:0] 0 hblktog5 _7 hblk toggle position 5 for v-sequence 7 [23:12] 0 hblktog6 _7 hblk toggle position 6 for v-sequence 7 bf [11:0] 0 clpobtog1 _7 clpob toggle position 1 for v-sequence 7 [23:12] 0 clpobtog2 _7 clpob toggle position 2 for v-sequence 7 table xlv. v-sequence 8 (vseq8) register map data bit default address content value register name description c0 [1:0] 0 hblkmask_8 masking polarity during hblk. h1 [0]. h3 [1]. [2] 0 clpobpol _8 clpobpol _8 clpobpol clpob start polarity [3] 0 pblkpol _8 pblkpol _8 pblkpol pblk start polarity [7:4] 0 vpatsel _8 vpatsel _8 vpatsel selected v-pattern group for v-sequence 8 [9:8] 0 vmask _8 vmask _8 vmask enable masking of v-outputs (specif ed by freeze/resume registers) [11:10] 0 hblkalt_8 enable hblk alternation [23:12] 0 unused unused c1 [11:0] 0 vpatrepo _8 number of selected v-pattern group repetitions for odd lines [23:12] 0 vpatrepe _8 number of selected v-pattern group repetitions for even lines c2 [11:0] 0 vpatstart _8 start position in the line for the selected v-pattern group [23:12] 0 hdlen _8 hd line length (number of pixels) for v-sequence 8 c3 [11:0] 0 pblktog1 _8 pblk toggle position 1 for v-sequence 8 [23:12] 0 pblktog2 _8 pblk toggle position 2 for v-sequence 8 c4 [11:0] 0 hblktog1 _8 hblk toggle position 1 for v-sequence 8 [23:12] 0 hblktog2 _8 hblk toggle position 2 for v-sequence 8 c5 [11:0] 0 hblktog3 _8 hblk toggle position 3 for v-sequence 8 [23:12] 0 hblktog4 _8 hblk toggle position 4 for v-sequence 8 c6 [11:0] 0 hblktog5 _8 hblk toggle position 5 for v-sequence 8 [23:12] 0 hblktog6 _8 hblk toggle position 6 for v-sequence 8 c7 [11:0] 0 clpobtog1 _8 clpob toggle position 1 for v-sequence 8 [23:12] 0 clpobtog2 _8 clpob toggle position 2 for v-sequence 8 rev. 0 obsolete
ad9995 C54 C table xlvi. v-sequence 9 (vseq9) register map data bit default address content value register name description c8 [1:0] 0 hblkmask_9 masking polarity during hblk. h1 [0]. h3 [1]. [2] 0 clpobpol _9 clpobpol _9 clpobpol clpob start polarity [3] 0 pblkpol _9 pblkpol _9 pblkpol pblk start polarity [7:4] 0 vpatsel _9 vpatsel _9 vpatsel selected v-pattern group for v-sequence 9 [9:8] 0 vmask _9 vmask _9 vmask enable masking of v-outputs (specif ed by freeze/resume registers) [11:10] 0 hblkalt_9 enable hblk alternation [23:12] 0 unused unused c9 [11:0] 0 vpatrepo _9 number of selected v-pattern group repetitions for odd lines [23:12] 0 vpatrepe _9 number of selected v-pattern group repetitions for even lines ca [11:0] 0 vpatstart _9 start position in the line for the selected v-pattern group [23:12] 0 hdlen _9 hd line length (number of pixels) for v-sequence 9 cb [11:0] 0 pblktog1 _9 pblk toggle position 1 for v-sequence 9 [23:12] 0 pblktog2 _9 pblk toggle position 2 for v-sequence 9 cc [11:0] 0 hblktog1 _9 hblk toggle position 1 for v-sequence 9 [23:12] 0 hblktog2 _9 hblk toggle position 2 for v-sequence 9 cd [11:0] 0 hblktog3 _9 hblk toggle position 3 for v-sequence 9 [23:12] 0 hblktog4 _9 hblk toggle position 4 for v-sequence 9 ce [11:0] 0 hblktog5 _9 hblk toggle position 5 for v-sequence 9 [23:12] 0 hblktog6 _9 hblk toggle position 6 for v-sequence 9 cf [11:0] 0 clpobtog1 _9 clpob toggle position 1 for v-sequence 9 [23:12] 0 clpobtog2 _9 clpob toggle position 2 for v-sequence 9 table xlvii. field 0 register map data bit default address content value register name description d0 [3:0] 0 vseqsel0_0 selected v-sequence for region 0. [4] 0 sweep0 _0 select sweep region for region 0. 0 = no sweep, 1= sweep. [5] 0 multi0 _0 select multiplier region for region 0. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel1_0 selected v-sequence for region 1. [10] 0 sweep1 _0 select sweep region for region 1. 0 = no sweep, 1 = sweep. [11] 0 multi1 _0 select multiplier region for region 1. 0 = no multiplier, 1 = multiplier. [15:12] 0 vseqsel2_0 selected v-sequence for region 2. [16] 0 sweep2 _0 select sweep region for region 2. 0 = no sweep, 1 = sweep. [17] 0 multi2 _0 select multiplier region for region 2. 0 = no multiplier, 1 = multiplier. [21:18] 0 vseqsel3_0 selected v-sequence for region 3. [22] 0 sweep3 _0 select sweep region for region 3. 0 = no sweep, 1 = sweep. [23] 0 multi3 _0 select multiplier region for region 3. 0 = no multiplier, 1 = multiplier. d1 [3:0] 0 vseqsel4_0 selected v-sequence for region 4. [4] 0 sweep4 _0 select sweep region for region 4. 0 = no sweep, 1 = sweep. [5] 0 multi4 _0 select multiplier region for region 4. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel5_0 selected v-sequence for region 5. [10] 0 sweep5 _0 select sweep region for region 5. 0 = no sweep, 1 = sweep. [11] 0 multi5 _0 select multiplier region for region 5. 0 = no multiplier, 1 = multiplier. [15:12] 0 vseqsel6_0 selected v-sequence for region 6. [16] 0 sweep6 _0 select sweep region for region 6. 0 = no sweep, 1 = sweep. [17] 0 multi6 _0 select multiplier region for region 6. 0 = no multiplier, 1 = multiplier. [23:18] unused unused. d2 [11:0] 0 scp1 _0 v-sequence change position #1 for field 0. [23:12] 0 scp2 _0 v-sequence change position #2 for field 0. d3 [11:0] 0 scp3 _0 v-sequence change position #3 for field 0. [23:12] 0 scp4 _0 v-sequence change position #4 for field 0. d4 [11:0] 0 vdlen _0 vd field length (number of lines) for field 0. [23:12] 0 hdlast _0 hd line length (number of pixels) for last line in field 0. rev. 0 obsolete
ad9995 C55 C table xlvii. field 0 register map (continued) data bit default address content value register name description d5 [3:0] 0 vpatsecond _0 selected second v-pattern group for vsg active line. [9:4] 0 sgmask _0 sgmask _0 sgmask masking of vsg outputs during vsg active line. [21:10] 0 sgpatsel _0 sgpatsel _0 sgpatsel selection of vsg patterns for each vsg output. d6 [11:0] 0 sgline1 _0 vsg active line 1. [23:12] 0 sgline2 _0 vsg active line 2 (if no second line needed, set to same as line 1 or max). d7 [11:0] 0 scp5 _0 v-sequence change position #5 for field 0. [23:12] 0 scp6 _0 v-sequence change position #6 for field 0. table xlviii. field 1 register map data bit default address content value register name description d8 [3:0] 0 vseqsel0_1 selected v-sequence for region 0. [4] 0 sweep0 _1 select sweep region for region 0. 0 = no sweep, 1 = sweep. [5] 0 multi0 _1 select multiplier region for region 0. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel1_1 selected v-sequence for region 1. [10] 0 sweep1 _1 select sweep region for region 1. 0 = no sweep, 1 = sweep. [11] 0 multi1 _1 select multiplier region for region 1. 0 = no multiplier, 1 = multiplier. [15:12] 0 vseqsel2_1 selected v-sequence for region 2. [16] 0 sweep2 _1 select sweep region for region 2. 0 = no sweep, 1 = sweep. [17] 0 multi2 _1 select multiplier region for region 2. 0 = no multiplier, 1 = multiplier. [21:18] 0 vseqsel3_1 selected v-sequence for region 3. [22] 0 sweep3 _1 select sweep region for region 3. 0 = no sweep, 1 = sweep. [23] 0 multi3 _1 select multiplier region for region 3. 0 = no multiplier, 1 = multiplier. d9 [3:0] 0 vseqsel4_1 selected v-sequence for region 4. [4] 0 sweep4 _1 select sweep region for region 4. 0 = no sweep, 1 = sweep. [5] 0 multi4 _1 select multiplier region for region 4. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel5_1 selected v-sequence for region 5. [10] 0 sweep5 _1 select sweep region for region 5. 0 = no sweep, 1 = sweep. [11] 0 multi5 _1 select multiplier region for region 5. 0 = no multiplier, 1 = multiplier. [15:12] 0 vseqsel6_1 selected v-sequence for region 6. [16] 0 sweep6 _1 select sweep region for region 6. 0 = no sweep, 1 = sweep. [17] 0 multi6 _1 select multiplier region for region 6. 0 = no multiplier, 1 = multiplier. [23:18] unused unused. da [11:0] 0 scp1 _1 v-sequence change position #1 for field 1. [23:12] 0 scp2 _1 v-sequence change position #2 for field 1. db [11:0] 0 scp3 _1 v-sequence change position #3 for field 1. [23:12] 0 scp4 _1 v-sequence change position #4 for field 1. dc [11:0] 0 vdlen _1 vd field length (number of lines) for field 1. [23:12] 0 hdlast _1 hd line length (number of pixels) for last line in field 1. dd [3:0] 0 vpatsecond _1 selected second v-pattern group for vsg active line. [9:4] 0 sgmask _1 sgmask _1 sgmask masking of vsg outputs during vsg active line. [21:10] 0 sgpatsel _1 sgpatsel _1 sgpatsel selection of vsg patterns for each vsg output. de [11:0] 0 sgline1 _1 vsg active line 1. [23:12] 0 sgline2 _1 vsg active line 2 (if no second line needed, set to same as line 1 or max). df [11:0] 0 scp5 _1 v-sequence change position #5 for field 1. [23:12] 0 scp6 _1 v-sequence change position #6 for field 1. rev. 0 obsolete
ad9995 C56 C table xlix. field 2 register map data bit default address content value register name description e0 [3:0] 0 vseqsel_2 selected v-sequence for region 0. [4] 0 sweep0 _2 select sweep region for region 0. 0 = no sweep, 1 = sweep. [5] 0 multi0 _2 select multiplier region for region 0. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel1_2 selected v-sequence for region 1. [10] 0 sweep1 _2 select sweep region for region 1. 0 = no sweep, 1 = sweep. [11] 0 multi1 _2 select multiplier region for region 1. 0 = no multiplier, 1 = multiplier. [15:12] 0 vseqsel2_2 selected v-sequence for region 2. [16] 0 sweep2 _2 select sweep region for region 2. 0 = no sweep, 1 = sweep. [17] 0 multi2 _2 select multiplier region for region 2. 0 = no multiplier, 1 = multiplier. [21:18] 0 vseqsel3_2 selected v-sequence for region 3. [22] 0 sweep3 _2 select sweep region for region 3. 0 = no sweep, 1 = sweep [23] 0 multi3 _2 select multiplier region for region 3. 0 = no multiplier, 1 = multiplier. e1 [3:0] 0 vseqsel4_2 selected v-sequence for region 4. [4] 0 sweep4 _2 select sweep region for region 4. 0 = no sweep, 1 = sweep. [5] 0 multi4 _2 select multiplier region for region 4. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel5_2 selected v-sequence for region 5. [10] 0 sweep5 _2 select sweep region for region 5. 0 = no sweep, 1 = sweep. [11] 0 multi5 _2 select multiplier region for region 5. 0 = no multiplier, 1 = multiplier. [15:12] 0 vseqsel6_2 selected v-sequence for region 6. [16] 0 sweep6 _2 select sweep region for region 6. 0 = no sweep, 1 = sweep. [17] 0 multi6 _2 select multiplier region for region 6. 0 = no multiplier, 1 = multiplier. [23:18] unused unused. e2 [11:0] 0 scp1 _2 v-sequence change position #1 for field 2. [23:12] 0 scp2 _2 v-sequence change position #2 for field 2. e3 [11:0] 0 scp3 _2 v-sequence change position #3 for field 2. [23:12] 0 scp4 _2 v-sequence change position #4 for field 2. e4 [11:0] 0 vdlen0 _2 vd field length (number of lines) for field 2. [23:12] 0 hdlast _2 hd line length (number of pixels) for last line in field 2. e5 [3:0] 0 vpatsecond _2 selected second v-pattern group for vsg active line. [9:4] 0 sgmask _2 sgmask _2 sgmask masking of vsg outputs during vsg active line. [21:10] 0 sgpatsel _2 sgpatsel _2 sgpatsel selection of vsg patterns for each vsg output. e6 [11:0] 0 sgline1 _2 vsg active line 1. [23:12] 0 sgline2 _2 vsg active line 2 (if no second line needed, set to same as line 1 or max). e7 [11:0] 0 scp5 _2 v-sequence change position #5 for field 2. [23:12] 0 scp6 _2 v-sequence change position #6 for field 2. table l. field 3 register map data bit default address content value register name description e8 [3:0] 0 vseqsel_3 selected v-sequence for region 0. [4] 0 sweep0 _3 select sweep region for region 0. 0 = no sweep, 1 = sweep. [5] 0 multi0 _3 select multiplier region for region 0. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel1_3 selected v-sequence for region 1. [10] 0 sweep1 _3 select sweep region for region 1. 0 = no sweep, 1 = sweep. [11] 0 multi1 _3 select multiplier region for region 1. 0 = no multiplier, 1 = multiplier. [15:12] 0 vseqsel2_3 selected v-sequence for region 2. [16] 0 sweep2 _3 select sweep region for region 2. 0 = no sweep, 1 = sweep. [17] 0 multi2 _3 select multiplier region for region 2. 0 = no multiplier, 1 = multiplier. [21:18] 0 vseqsel3_3 selected v-sequence for region 3. [22] 0 sweep3 _3 select sweep region for region 3. 0 = no sweep, 1 = sweep. [23] 0 multi3 _3 select multiplier region for region 3. 0 = no multiplier, 1 = multiplier. rev. 0 obsolete
ad9995 C57 C table l. field 3 register map (continued) data bit default address content value register name description e9 [3:0] 0 vseqsel4_3 selected v-sequence for region 4. [4] 0 sweep4 _3 select sweep region for region 4. 0 = no sweep, 1 = sweep. [5] 0 multi4 _3 select multiplier region for region 4. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel5_3 selected v-sequence for region 5. [10] 0 sweep5 _3 select sweep region for region 5. 0 = no sweep, 1 = sweep. [11] 0 multi5 _3 select multiplier region for region 5. 0 = no multiplier, 1 = multiplier. [15:12] 0 vseqsel6_3 selected v-sequence for region 6. [16] 0 sweep6 _3 select sweep region for region 6. 0 = no sweep, 1 = sweep. [17] 0 multi6 _3 select multiplier region for region 6. 0 = no multiplier, 1 = multiplier. [23:18] unused unused. ea [11:0] 0 scp1 _3 v-sequence change position #1 for field 3. [23:12] 0 scp2 _3 v-sequence change position #2 for field 3. eb [11:0] 0 scp3 _3 v-sequence change position #3 for field 3. [23:12] 0 scp4 _3 v-sequence change position #4 for field 3. ec [11:0] 0 vdlen _3 vd field length (number of lines) for field 3. [23:12] 0 hdlast _3 hd line length (number of pixels) for last line in field 3. ed [3:0] 0 vpatsecond _3 selected second v-pattern group for vsg active line. [9:4] 0 sgmask _3 sgmask _3 sgmask masking of vsg outputs during vsg active line. [21:10] 0 sgpatsel _3 sgpatsel _3 sgpatsel selection of vsg patterns for each vsg output. ee [11:0] 0 sgline1 _3 vsg active line 1. [23:12] 0 sgline2 _3 vsg active line 2 (if no second line needed, set to same as line 1 or max). ef [11:0] 0 scp5 _3 v-sequence change position #5 for field 3. [23:12] 0 scp6 _3 v-sequence change position #6 for field 3. table li. field 4 register map data bit default address content value register name description f0 [3:0] 0 vseqsel0 _4 selected v-sequence for region 0. [4] 0 sweep0_4 select sweep region for region 0. 0 = no sweep, 1 = sweep. [5] 0 multi0_4 select multiplier region for region 0. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel1 _4 selected v-sequence for region 1. [10] 0 sweep1_4 select sweep region for region 1. 0 = no sweep, 1 = sweep. [11] 0 multi1_4 select multiplier region for region 1. 0 = no multiplier, 1 = multiplier. [15:12] 0 vseqsel2 _4 selected v-sequence for region 2. [16] 0 sweep2_4 select sweep region for region 2. 0 = no sweep, 1 = sweep. [17] 0 multi2_4 select multiplier region for region 2. 0 = no multiplier, 1 = multiplier. [21:18] 0 vseqsel3 _4 selected v-sequence for region 3. [22] 0 sweep3_4 select sweep region for region 3. 0 = no sweep, 1 = sweep. [23] 0 multi3_4 select multiplier region for region 3. 0 = no multiplier, 1 = multiplier. f1 [3:0] 0 vseqsel4 _4 selected v-sequence for region 4. [4] 0 sweep4_4 select sweep region for region 4. 0 = no sweep, 1 = sweep. [5] 0 multi4_4 select multiplier region for region 4. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel5 _4 selected v-sequence for region 5. [10] 0 sweep5_4 select sweep region for region 5. 0 = no sweep, 1 = sweep. [11] 0 multi5_4 select multiplier region for region 5. 0 = no multiplier, 1 = multiplier.. [15:12] 0 vseqsel6 _4 selected v-sequence for region 6. [16] 0 sweep6_4 select sweep region for region 6. 0 = no sweep, 1 = sweep. [17] 0 multi6_4 select multiplier region for region 6. 0 = no multiplier, 1 = multiplier. [23:18] unused unused. f2 [11:0] 0 scp1_4 v-sequence change position #1 for field 4. [23:12] 0 scp2_4 v-sequence change position #2 for field 4. f3 [11:0] 0 scp3_4 v-sequence change position #3 for field 4. [23:12] 0 scp4_4 v-sequence change position #4 for field 4. rev. 0 obsolete
ad9995 C58 C table li. field 4 register map (continued) data bit default address content value register name description f4 [11:0] 0 vdlen_4 vd field length (number of lines) for field 4. [23:12] 0 hdlast_4 hd line length (number of pixels) for last line in field 4. f5 [3:0] 0 vpatsecond_4 selected second v-pattern group for vsg active line. [9:4] 0 sgmask_4 masking of vsg outputs during vsg active line. [21:10] 0 sgpatsel_4 selection of vsg patterns for each vsg output. f6 [11:0] 0 sgline1_4 vsg active line 1. [23:12] 0 sgline2_4 vsg active line 2 (if no second line needed, set to same as line 1 or max). f7 [11:0] 0 scp5_4 v-sequence change position #5 for field 4. [23:12] 0 scp6_4 v-sequence change position #6 for field 4. table lii. field 5 register map data bit default address content value register name description f8 [3:0] 0 vseqsel0 _5 selected v-sequence for region 0. [4] 0 sweep0_5 select sweep region for region 0. 0 = no sweep, 1 = sweep. [5] 0 multi0_5 select multiplier region for region 0. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel1 _5 selected v-sequence for region 1. [10] 0 sweep1_5 select sweep region for region 1. 0 = no sweep, 1 = sweep. [11] 0 multi1_5 select multiplier region for region 1. 0 = no multiplier, 1 = multiplier. [15:12] 0 vseqsel2 _5 selected v-sequence for region 2. [16] 0 sweep2_5 select sweep region for region 2. 0 = no sweep, 1 = sweep. [17] 0 multi2_5 select multiplier region for region 2. 0 = no multiplier, 1 = multiplier. [21:18] 0 vseqsel3 _5 selected v-sequence for region 3. [22] 0 sweep3_5 select sweep region for region 3. 0 = no sweep, 1 = sweep. [23] 0 multi3_5 select multiplier region for region 3. 0 = no multiplier, 1 = multiplier. f9 [3:0] 0 vseqsel4 _5 selected v-sequence for region 4. [4] 0 sweep4_5 select sweep region for region 4. 0 = no sweep, 1 = sweep [5] 0 multi4_5 select multiplier region for region 4. 0 = no multiplier, 1 = multiplier. [9:6] 0 vseqsel5 _5 selected v-sequence for region 5. [10] 0 sweep5_5 select sweep region for region 5. 0 = no sweep, 1 = sweep. [11] 0 multi5_5 select multiplier region for region 5. 0 =no multiplier, 1 = multiplier. [15:12] 0 vseqsel6 _5 selected v-sequence for region 6. [16] 0 sweep6_5 select sweep region for region 6. 0 = no sweep, 1 = sweep. [17] 0 multi6_5 select multiplier region for region 6. 0 = no multiplier, 1 = multiplier. [23:18] unused unused. fa [11:0] 0 scp1_5 v-sequence change position #1 for field 5. [23:12] 0 scp2_5 v-sequence change position #2 for field 5. fb [11:0] 0 scp3_5 v-sequence change position #3 for field 5. [23:12] 0 scp4_5 v-sequence change position #4 for field 5. fc [11:0] 0 vdlen_5 vd field length (number of lines) for field 5. [23:12] 0 hdlast_5 hd line length (number of pixels) for last line in field 5. fd [3:0] 0 vpatsecond_5 selected second v-pattern group for vsg active line. [9:4] 0 sgmask_5 masking of vsg outputs during vsg active line. [21:10] 0 sgpatsel_5 selection of vsg patterns for each vsg output. fe [11:0] 0 sgline1_5 vsg active line 1. [23:12] 0 sgline2_5 vsg active line 2 (if no second line needed, set to same as line 1 or max). ff [11:0] 0 scp5_5 v-sequence change position #5 for field 5. [23:12] 0 scp6_5 v-sequence change position #6 for field 5. rev. 0 obsolete
ad9995 C59 C outline dimensions 56-lead lead frame chip scale package [lfcsp] 8 mm 8 mm body (cp-56) dimensions shown in millimeters pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 2 9 bottom view 6.25 6.10 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 nom 1.00 0.90 0.80 6.50 ref seating plane 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 sq 0.05 max 0.02 nom 0.25 min compliant to jedec standards mo-220-vlld-2 rev. 0 obsolete
c04336C0C8/03(0) C60 C obsolete

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